AM6548BACDXEAF datasheet(187/282 Pages) TI

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(4)

H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(5)

(5)

GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

7.9.5.10.2.2 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode

NO.

PARAMETER

DESCRIPTION

MODE(15)

MIN

MAX UNIT

FA0

tw(be[x]nV)

Pulse duration, output lower-byte enable and

command latch enable GPMC_BE0n_CLE, output

upper-byte enable GPMC_BE1n valid time

Read

0+N (12)

Write

0+N (12)

FA1

tw(csnV)

Pulse duration, output chip select GPMC_CSn[x]

(13) low

Read

0+A (1)

Write

0+A (1)

FA3

td(csnV-advnIV)

Delay time, output chip select GPMC_CSn[x](13)

valid to output address valid and address latch

enable GPMC_ADVn_ALE invalid

Read

-2+B (2)

2+B (2)

Write

-2+B (2)

2+B (2)

FA4

td(csnV-oenIV)

Delay time, output chip select GPMC_CSn[x](13)

valid to output enable GPMC_OEn_REn invalid

(Single read)

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

-2+C (3)

2+C (3)

FA9

td(aV-csnV)

Delay time, output address GPMC_A[27:1] valid to

output chip select GPMC_CSn[x](13) valid

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

-2+J (9)

2+J (9)

FA10 td(be[x]nV-csnV)

Delay time, output lower-byte enable and

command latch enable GPMC_BE0n_CLE, output

upper-byte enable GPMC_BE1n valid to output

chip select GPMC_CSn[x](13) valid

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

-2+J (9)

2+J (9)

FA12 td(csnV-advnV)

Delay time, output chip select GPMC_CSn[x](13)

valid to output address valid and address latch

enable GPMC_ADVn_ALE valid

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

-2+K (10)

2+K (10)

FA13 td(csnV-oenV)

Delay time, output chip select GPMC_CSn[x](13)

valid to output enable GPMC_OEn_REn valid

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

-2+L (11)

2+L (11)

FA16 tw(aIV)

Pulse duration output address GPMC_A[26:1]

invalid between 2 successive read and write

accesses

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

0+G (7)

FA18 td(csnV-oenIV)

Delay time, output chip select GPMC_CSn[x](13)

valid to output enable GPMC_OEn_REn invalid

(Burst read)

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

-2+I (8)

2+I (8)

FA20 tw(aV)

Pulse duration, output address GPMC_A[27:1]

valid - 2nd, 3rd, and 4th accesses

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

0+D (4)

FA25 td(csnV-wenV)

Delay time, output chip select GPMC_CSn[x](13)

valid to output write enable GPMC_WEn valid

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

-2+E (5)

2+E (5)

FA27 td(csnV-wenIV)

Delay time, output chip select GPMC_CSn[x](13)

valid to output write enable GPMC_WEn invalid

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

-2+F (6)

2+F (6)

FA28 td(wenV-dV)

Delay time, output write enable GPMC_WEn valid

to output data GPMC_AD[15:0] valid

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

2.8

FA29 td(dV-csnV)

Delay time, output data GPMC_AD[15:0] valid to

output chip select GPMC_CSn[x](13) valid

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

-2+J (9)

2+J (9)

FA37 td(oenV-aIV)

Delay time, output enable GPMC_OEn_REn valid

to output address GPMC_AD[15:0] phase end

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

2.8

(1)

For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

with n being the page burst access number

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AM6548, AM6528, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

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AM6548BACDXEAF Datasheet(PDF) 187 Page - Texas Instruments

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