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AM6548BACDXEAF Datasheet(PDF) 232 Page - Texas Instruments |
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AM6548BACDXEAF Datasheet(HTML) 232 Page - Texas Instruments |
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232 / 282 page  NO. MIN MAX UNIT PRSD4 th(SD_CLK-SD_DATA) Hold time, SD_DATA valid before SD_CLK active edge 5 ns SDx_CLK SPRSP08_TIMING_PRU_07 PRSD2H PRSD2L PRSD4 PRSD3 SDx_D PRSD1 Figure 7-100. PRU_ICSSG PRU SD_CLK Falling Active Edge SDx_CLK PRSD2L PRSD3 PRSD4 SPRSP08_TIMING_PRU_08 SDx_D Figure 7-101. PRU_ICSSG PRU SD_CLK Rising Active Edge 7.9.5.21.1.4.2 PRU_ICSSG PRU Timing Requirements - Peripheral Interface Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT PRPIF1 tw(PIF_DATA_INH) Pulse Duration, PIF_DATA_IN High 2 + 0.475× (4×P) (1) ns PRPIF2 tw(PIF_DATA_INL) Pulse Duration, PIF_DATA_IN Low 2 + 0.475× (4×P) (1) ns (1) P = 1x (or TX) clock period, defined by TX_DIV_FACTOR and TX_DIV_FACTOR_FRAC in the CFG_ED_Pn_TXCFG register. PIF_DATA_IN PRPIF1 SPRSP08_TIMING_PIF_01 PRPIF2 Figure 7-102. PRU_ICSSG PRU Peripheral Interface Timing 7.9.5.21.1.4.3 PRU_ICSSG PRU Switching Characteristics - Peripheral Interface Mode NO. DESCRIPTION MIN MAX UNIT PRPIF1 tc(PIF_CLK) Cycle time, PIF_CLK 30 ns PRPIF2H tw(PIF_DATA_INH) Pulse Duration, PIF_CLK High 0 + 0.475×P (1) ns PRPIF2L tw(PIF_DATA_INL) Pulse Duration, PIF_CLK Low 0 + 0.475×P (1) ns PRPIF3 td(PIF_CLK- PIF_DATA_OUT) Delay time, PIF_CLK fall to PIF_DATA_OUT -5 5 ns AM6548, AM6528, AM6526 SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021 www.ti.com 232 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AM6548 AM6528 AM6526 |
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