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IS61NVP102418-200B3 Datasheet(PDF) 15 Page - Integrated Silicon Solution, Inc |
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IS61NVP102418-200B3 Datasheet(HTML) 15 Page - Integrated Silicon Solution, Inc |
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15 / 35 page ![]() Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 15 Rev. G 07/10/06 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI® READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -250 -200 Symbol Parameter Min. Max. Min. Max. Unit fmax Clock Frequency — 250 — 200 MHz tKC Cycle Time 4.0 — 5 — ns tKH Clock High Time 1.7 — 2 — ns tKL Clock Low Time 1.7 — 2 — ns tKQ Clock Access Time — 2.6 — 3.1 ns tKQX(2) Clock High to Output Invalid 0.8 — 1.5 — ns tKQLZ(2,3) Clock High to Output Low-Z 0.8 — 1 — ns tKQHZ(2,3) Clock High to Output High-Z — 2.6 — 3.0 ns tOEQ Output Enable to Output Valid — 2.8 — 3.1 ns tOELZ(2,3) Output Enable to Output Low-Z 0 — 0 — ns tOEHZ(2,3) Output Disable to Output High-Z — 2.6 — 3.0 ns tAS Address Setup Time 1.2 — 1.4 — ns tWS Read/Write Setup Time 1.2 — 1.4 — ns tCES Chip Enable Setup Time 1.2 — 1.4 — ns tSE Clock Enable Setup Time 1.2 — 1.4 — ns tADVS Address Advance Setup Time 1.2 — 1.4 — ns tDS Data Setup Time 1.2 — 1.4 — ns tAH Address Hold Time 0.3 — 0.4 — ns tHE Clock Enable Hold Time 0.3 — 0.4 — ns tWH Write Hold Time 0.3 — 0.4 — ns tCEH Chip Enable Hold Time 0.3 — 0.4 — ns tADVH Address Advance Hold Time 0.3 — 0.4 — ns tDH Data Hold Time 0.3 — 0.4 — ns tPDS ZZ High to Power Down — 2 — 2 cyc tPUS ZZ Low to Power Down — 2 — 2 cyc Notes: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. |
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