IS61NVP102418-200B3 datasheet(25/35 Pages) ISSI

Part #	IS61NVP102418-200B3

Description	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM

PDF	35 Pages

Scroll/Zoom	100%

Manufacturer	ISSI [Integrated Silicon Solution, Inc]

Direct Link	http://www.issi.com

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25 / 35 page

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

25

Rev. G

07/10/06

IS61NLP25672/IS61NVP25672

IS61NLP51236/IS61NVP51236

IS61NLP102418/IS61NVP102418

ISSI®

INSTRUCTION CODES

Code

Instruction

Description

000

EXTEST

Captures the Input/Output ring contents. Places the boundary scan register between

the TDI and TDO. Forces all SRAM outputs to High-Z state. This

instruction is not 1149.1 compliant.

001

IDCODE

Loads the ID register with the vendor ID code and places the register between

TDI and TDO. This operation does not affect SRAM operation.

010

SAMPLE-Z

Captures the Input/Output contents. Places the boundary scan register between TDI

and TDO. Forces all SRAM output drivers to a High-Z state.

011

RESERVED

Do Not Use: This instruction is reserved for future use.

100

SAMPLE/PRELOAD

Captures the Input/Output ring contents. Places the boundary scan register between

TDI and TDO. Does not affect the SRAM operation. This instruction does not implement

1149.1 preload function and is therefore not 1149.1 compliant.

101

RESERVED

Do Not Use: This instruction is reserved for future use.

110

RESERVED

Do Not Use: This instruction is reserved for future use.

111

BYPASS

Places the bypass register between TDI and TDO. This operation does not

affect SRAM operation.

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

Test Logic Reset

Run Test/Idle

11

1

11

1

0

1

00

0

10

TAP CONTROLLER STATE DIAGRAM

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IS61NVP102418-200B3 Datasheet(PDF) 25 Page - Integrated Silicon Solution, Inc

IS61NVP102418-200B3 Datasheet(HTML) 25 Page - Integrated Silicon Solution, Inc

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