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IS61NVP102418-200B3 Datasheet(PDF) 26 Page - Integrated Silicon Solution, Inc |
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IS61NVP102418-200B3 Datasheet(HTML) 26 Page - Integrated Silicon Solution, Inc |
26 / 35 page ![]() 26 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI® TAP Electrical Characteristics Over the Operating Range(1,2) Symbol Parameter Test Conditions Min. Max. Units VOH1 Output HIGH Voltage IOH = –2.0 mA 1.7 — V VOH2 Output HIGH Voltage IOH = –100 µA 2.1 — V VOL1 Output LOW Voltage IOL = 2.0 mA — 0.7 V VOL2 Output LOW Voltage IOL = 100 µA — 0.2 V VIH Input HIGH Voltage 1.7 VDD +0.3 V VIL Input LOW Voltage –0.3 0.7 V IX Input Leakage Current VSS ≤ V I ≤ VDDQ –10 10 µA Notes: 1. All Voltage referenced to Ground. 2. Overshoot: VIH (AC) ≤ VDD +1.5V for t ≤ tTCYC/2, Undershoot: VIL (AC) ≤ 0.5V for t ≤ tTCYC/2, Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms. TAP AC ELECTRICAL CHARACTERISTICS(1,2) (OVER OPERATING RANGE) Symbol Parameter Min. Max. Unit tTCYC TCK Clock cycle time 100 — ns fTF TCK Clock frequency — 10 MHz tTH TCK Clock HIGH 40 — ns tTL TCK Clock LOW 40 — ns tTMSS TMS setup to TCK Clock Rise 10 — ns tTDIS TDI setup to TCK Clock Rise 10 — ns tCS Capture setup to TCK Rise 10 — ns tTMSH TMS hold after TCK Clock Rise 10 — ns tTDIH TDI Hold after Clock Rise 10 — ns tCH Capture hold after Clock Rise 10 — ns tTDOV TCK LOW to TDO valid — 20 ns tTDOX TCK LOW to TDO invalid 0 — ns Notes: 1. Both tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. |
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