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IS61NVP102418-200B3 Datasheet(PDF) 4 Page - Integrated Silicon Solution, Inc |
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IS61NVP102418-200B3 Datasheet(HTML) 4 Page - Integrated Silicon Solution, Inc |
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4 / 35 page  4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI® PIN CONFIGURATION — 256K X 72, 209-Ball PBGA (TOP VIEW) 12 34 56 78 9 10 11 A DQg DQg A CE2 A ADV A CE2 A DQb DQb B DQg DQg BWc BWgNC WE A BWb BWf DQb DQb C DQg DQg BWh BWdNC CE NC BWe BWa DQb DQb D DQg DQg VSS NC NC OE NC NC VSS DQb DQb E DQPg DQPc VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPf DQPb F DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf G DQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf H DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf J DQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf K NC NC CLK NC VSS CKE VSS NC NC NC NC L DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa M DQh DQh VSS VSS VSS NC VSS VSS VSS DQa DQa N DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa P DQh DQh VSS VSS VSS ZZ VSS VSS VSS DQa DQa R DQPd DQPh VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPa DQPe T DQd DQd VSS NC NC MODE NC NC VSS DQe DQe U DQd DQd NC A NC A NC A NC DQe DQe V DQd DQd A A A A1 A A A DQe DQe W DQd DQd TMS TDI A A0 A TDO TCK DQe DQe 11 x 19 Ball BGA—14 x 22 mm2 Body—1 mm Ball Pitch PIN DESCRIPTIONS Symbol Pin Name A Synchronous Address Inputs A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. ADV Synchronous Burst Address Advance BWa-BWh Synchronous Byte Write Enable CE, CE2, CE2 Synchronous Chip Enable CLK Synchronous Clock CKE Clock Enable DQx Synchronous Data Input/Output DQPx Parity Data I/O VSS Ground MODE Burst Sequence Selection OE Output Enable TCK, TDI JTAG Pins TDO, TMS VDD 3.3V/2.5V Power Supply VDDQ Isolated Output Buffer Supply: 3.3V/2.5V WE Write Enable ZZ Snooze Enable |
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Similar Description - IS61NVP102418-200B3 |
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