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IS61NVP102418-200B3 Datasheet(PDF) 6 Page - Integrated Silicon Solution, Inc |
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IS61NVP102418-200B3 Datasheet(HTML) 6 Page - Integrated Silicon Solution, Inc |
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6 / 35 page  6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI® 165-PIN PBGA PACKAGE CONFIGURATION 1024K x 18 (TOP VIEW) PIN DESCRIPTIONS Symbol Pin Name A Address Inputs A0, A1 Synchronous Burst Address Inputs ADV Synchronous Burst Address Advance/ Load WE Synchronous Read/Write Control Input CLK Synchronous Clock CKE Clock Enable CE, CE2, CE2 Synchronous Chip Enable BWx (x=a,b) Synchronous Byte Write Inputs OE Output Enable ZZ Power Sleep Mode 123456789 10 11 A A BWb CKE BNC A WE OE CNC NC Vss Vss DNC DQb Vss Vss NC ENC DQb Vss Vss Vss F NC DQb NC GNC DQb NC NC HNC VDD VDDQ J DQb NC DQa K DQb NC L DQb NC Vss M DQb NC Vss N DQPb NC Vss Vss NC PNC NC A1* TDO R MODE A TCK CE2 Vss Vss Vss Vss Vss Vss Vss Vss NC NC A A A A A A A A A A A A A A A CE VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ NC NC VDD VDD VDD VDD VDD VDD VDD VDD VDD NC BWa Vss Vss Vss Vss Vss Vss Vss Vss NC TDI TMS CE2 CLK Vss NC A0* NC Vss Vss Vss Vss Vss Vss ADV VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ NC NC NC DQa DQa DQa NC NC NC NC NC NC NC ZZ DQa DQa DQa DQa DQPa Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. MODE Burst Sequence Selection TCK, TDI JTAG Pins TDO, TMS VDD 3.3V/2.5V Power Supply NC No Connect DQx Data Inputs/Outputs DQPx Parity Data I/O VDDQ Isolated output Power Supply 3.3V/2.5V VSS Ground |
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