ADE5166 datasheet(132/148 Pages) AD

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ADE5166/ADE5169

Rev. 0 | Page 132 of 148

Table 153. SPI Configuration SFR 1 (SPIMOD1, Address 0xE8)

Bit

Bit Address

Mnemonic

Default

Description

[7:6]

0xEF to 0xEE

Reserved

Reserved.

0xED

INTMOD

SPI interrupt mode.

INTMOD

Result

SPI interrupt is set when the SPI Rx buffer is full

SPI interrupt is set when the SPI Tx buffer is empty

0xEC

AUTO_SS

Master mode, SS output control (see

Figure 106

AUTO_SS

Result

The SS pin is held low while this bit is cleared, allowing manual chip select

control using the SS pin

Single byte read or write; the SS pin goes low during a single byte

transmission and then returns high

Continuous transfer; the SS pin goes low during the duration of the

multibyte continuous transfer and then returns high

0xEB

SS_EN

Slave mode, SS input enable.

When this bit is set to Logic 1, the SS pin is defined as the slave select input pin for the

SPI slave interface.

0xEA

RxOFW

Receive buffer overflow write enable.

RxOFW

Result

If the SPI2CRx SFR has not been read when a new data byte is received,

the new byte is discarded

If the SPI2CRx SFR has not been read when a new data byte is received,

the new byte overwrites the old data

[1:0]

0xE9 to 0xE8

SPIR

Master mode, SPI SCLK frequency.

SPIR

Result

fCORE/8 = 512 kHz (if fCORE = 4.096 MHz)

fCORE/16 = 256 kHz (if fCORE = 4.096 MHz)

fCORE/32 = 128 kHz (if fCORE = 4.096 MHz)

fCORE/64 = 64 kHz (if fCORE = 4.096 MHz)

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