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L9777B13TR Datasheet(PDF) 7 Page - STMicroelectronics |
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L9777B13TR Datasheet(HTML) 7 Page - STMicroelectronics |
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7 / 25 page  L9777 Block diagrams and pins configuration Doc ID 13496 Rev 2 7/25 Figure 5. Package pin configuration (option C) Table 2. Pin description Pin# I/O Name Function 1 O RESET/VDD_LOW OPTION A & B: RESET output. This pin is set low if NMI output goes low for adjustable filter time OPTION C: VDD_LOW output This pin is set low when undervoltage on VDD is detected 2O NMI Non maskable Interrupt Output This pin is set low when low voltage on VCC is detected or frequency of WD signal is too low. 3I D NMI/RESET power up delay. External cap on this pin sets the time response of the VCC low voltage detector and the time response of the watchdog monitor. 4 I VDD_EN VDD control. OPTION A: If this pin is low VDD output voltage is not available (connect this pin to VCC or left floating to switch on VDD output voltage) OPTION B & C: If this pin is low or left floating VDD output voltage is not available (connect this pin to VCC to switch on VDD regulator) 5I WD Watchdog input. If the frequency at this input pin is too low, the NMI output is activated low 6I WD_EN Watchdog function enable/disable OPTION A: If this pin is low the watchdog function is disabled, if connected to VCC or left floating the watchdog function is enabled. OPTION B & C: If this pin is low or floating, the watchdog function is disabled, if connected to VCC the watchdog function is enabled. 7I VI Input voltage Block to GND with a capacitor of value at least 100 nF VDD_LOW NMI D VDD_EN WD WD_EN VI N.C. VCC VDD GND RADJ 1 3 2 4 5 6 10 9 8 7 11 12 PinConfC |
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