Functional description

L9777

12/25

DocID13496 Rev 4

In both cases, if the output voltage VCC becomes lower than 2.0V (typ) than NMI may go

immediately low without any delay. The NMI low signal is guaranteed for an output voltage

VCC greater than 1V.

When VCC returns over VCCUN threshold NMI goes high with a filter time TRD. This time is

obtained by 127 period of an oscillator with an additional initial time. The oscillator period is

given by:

TOSC

VDU VDRL

–

 CD





IRC

-----------------------------------------------------------

VDU VDRL

–

 CD





IRD

-----------------------------------------------------------

+

=

where:

ICR = 20 μA (typ) is a current internally generated,

IDR = 20 μA (typ) is a current internally generated,

VDU = 1.24 V and VDRL = 0.62 V are two typical internal thresholds,

CD is the external capacitance on pin D.

TRD is given by:

TRD (s) = T0 + 127 x TOSC = 0.62*10-3 + 7.874* 106 * CD (typ)

Where T0 is the initial ramp between 0 V and VDU as in Figure 8.

Figure 8. Reset time diagram

If NMI output goes to 0 V for filter time TRESDF (which is fixed by external cap on TIMING

pin) also the RESET signal goes to 0 V. RESET low signal is guaranteed for VCC > 1 V.

Figure 9. Filter time between NMI and RESET