Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of
−40°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree†
Fully Static Operation
Buffered Inputs
Common Reset
Positive Edge Clocking
Typical fmax = 60 MHz at VCC = 5 V,
CL = 15 pF, TA = 25°C
Fanout (Over Temperature Range)
− Standard Outputs . . . 10 LSTTL Loads
− Bus Driver Outputs . . . 15 LSTTL Loads
Balanced Propagation Delay and Transition
Times
Significant Power Reduction Compared to
LSTTL Logic ICs
VCC Voltage = 2 V to 6 V
High Noise Immunity NIL or NIH = 30% of
VCC, VCC = 5 V

description/ordering information
The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each
of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of
the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and
can be used in conjunction with the clock enable (CE) input to cascade several stages. CE disables counting
when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded
outputs, except output 0, to low.
The device can drive up to ten low-power Schottky equivalent loads.