TLV5734

TRIPLE 8BIT 30MSPS ADC WITH HIGH

PRECISION CLAMP FOR YUV/RGB VIDEO

SLES026A – APRIL 2002 – REVISED JANUARY 2003

4

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

I/O

TYPE†

DESCRIPTION

NAME

NO.

I/O

TYPE†

DESCRIPTION

A AVCC

62

I

A

Analog supply (3.3 V) for ADC A

AD8–AD1

6–13

O

D

Data output of ADC A (MSB:AD8, LSB:AD1) (format 1, format 2, format 3)

AGND

45

I

A

Substrate ground

AIN

63

I

A

Analog input of ADC A. Used for G/Y

B AVCC

55

I

A

Analog supply (3.3 V) for ADC B

BD8–BD1

17–24

O

D

Data output of ADC B (MSB:BD8, LSB:BD1) (format 2)

Data output of ADC B, C (format 1, format 3)

BIN

56

I

A

Analog input of ADC B. Uses for B/U

C AVCC

50

I

A

Analog supply (3.3 V) for ADC C

CD8–CD1

36–43

O

D

Data output of ADC C (MSB:CD8, LSB:CD1) (format 2)

When MODE1 = L, MODE0 = L, CD8 outputs MSB flag of BD8–BD5 (format 1)

When MODE1 = L, MODE0 = L, CD7 outputs LSB flag of BD8–BD5 (format 1)

When MODE1 = H, MODE0 = L, CD8 outputs B channel flag of BD8–BD1 (format 3)

When MODE1 = H, MODE0 = L, CD7 outputs B channel flag of BD8–BD1 (CD8–CD1) (format 3)

CIN

51

I

A

Analog input of ADC C. Used for R/V

CLK

31

I

D

Clock input. The clock frequency is four times the frequency subcarrier (fsc) for most video

systems (see Table 3).

CLP OUT A

60

O

A

Clamp bias current of ADC A. A resistor-capacitor network sets the clamp settling time.

CLP OUT B

53

O

A

Clamp bias current of ADC B. A resistor-capacitor network sets the clamp settling time.

CLP OUT C

48

O

A

Clamp bias current of ADC C. A resistor-capacitor network sets the clamp settling time.

CLPV A

61

I

A

Clamp level of ADC A (see Table 1)

CLPV B

54

I

A

Clamp level of ADC B (see Table 1)

CLPV C

49

I

A

Clamp level of ADC C (see Table 1)

DGND

15

I

D

Digital ground for all logic

DVDD‡

26

I

D

Digital supply (3.3 V) for all logic. DVDD, QA DVDD, QB DVDD, and QC DVDD are tied together

internally.

EXTCLP

3

I

D

External clamp pulse input (active high)

GND A

64

I

A

Analog ground of ADC A

GND B

57

I

A

Analog ground of ADC B

GND C

52

I

A

Analog ground of ADC C

G/Y

33

I

D

Video input mode selector, low for RGB, high for YUV

INIT

30

I

D

Output initialized. The output data is synchronized with the first falling edge of CLK after INIT

changes from low to high (see Figure 1). INIT is a control terminal that allows the external system

to initialize the TLV5734 data conversion cycle.

MODE1,0

28,29

I

D

Output format mode selector (see Table 4)

NC

32

I

D

NC should be tied low when using this device.

OEB A

4

I

D

Output enable of ADC A (active low)

OEB B

27

I

D

Output enable of ADC B (active low)

OEB C

34

I

D

Output enable of ADC C (active low)

QA DGND

5

I

D

Digital ground for output driver of ADC A

QA DVDD‡

14

I

D

Digital supply (3.3 V) for output driver of ADC A. DVDD, QA DVDD, QB DVDD, and QC DVDD are

tied together internally.

QB DGND

25

I

D

Digital ground for output driver of ADC B

† A = analog pin, D = digital pin

‡ These pins should be driven from the same power supply.