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MM54HC4017 Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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MM54HC4017 Datasheet(HTML) 3 Page - National Semiconductor (TI) |
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3 / 6 page  AC Electrical Characteristics VCCe5V TAe25 C CLe15 pF tretfe6ns Symbol Parameter Conditions Typ Guaranteed Units Limit fMAX Maximum Clock Frequency Measured with 50 30 MHz respect to carry line tPHL tPLH Maximum Propagation 26 44 ns Delay Enable to Carry-Out Line tPHL tPLH Maximum Propagation 27 44 ns Delay Enable Decode-Out Lines tPHL tPLH Maximum Propagation 23 40 ns Delay Reset or Clock to Decode Out tPHL tPLH Maximum Propagation 23 40 ns Delay Reset or Clock to Carry Out tS Minimum Clock Inhibit to Clock 12 20 ns Set-Up Time tW Minimum Clock or Reset Pulse Width 8 16 ns tREM Minimum Reset Removal Time 20 10 ns AC Electrical Characteristics VCCe20–60V CLe50 pF tretfe6 ns (unless otherwise specified) TAe25 C 74HC 54HC Symbol Parameter Conditions VCC TAeb40 to 85 CTAeb55 to 125 C Units Typ Guaranteed Limits fMAX Maximum Clock Frequency Measured with 20V 6 5 4 MHz respect to carry line 45V 30 24 20 MHz 60V 35 28 24 MHz tPHL tPLH Maximum Propagation 20V 89 250 312 375 ns Delay Enable to Carry-Out Line 45V 25 50 63 75 ns 60V 20 43 54 65 ns tPHL tPLH Maximum Propagation 20V 90 250 312 375 ns Delay Enable to Decode Out Line 45V 25 50 63 75 ns 60V 20 43 54 65 ns tPHL tPLH Maximum Propagation 20V 82 230 288 345 ns Delay Reset or Clock to Decode Out 45V 22 46 58 69 ns 60V 18 39 49 59 ns tPHL tPLH Maximum Propagation 20V 82 230 288 345 ns Delay Reset or Clock to Carry Out 45V 22 46 58 69 ns 60V 18 39 49 59 ns tW Minimum Reset Clock or 20V 30 80 100 120 ns Clock Enable Pulse Width 45V 9 16 20 24 ns 60V 8 14 18 21 ns tREM Minimum Reset Removal Time 20V 100 125 150 ns 45V 20 25 30 ns 60V 17 21 25 ns tS tH Minimum Clock Inhibit 20V 50 63 75 ns to Clock Set-Up or Hold Time 45V 10 13 15 ns 60V 9 11 13 ns tTHL tTLH Maximum Output Rise 20V 30 75 95 110 ns and Fall Time 45V 8 15 19 22 ns 60V 7 13 16 19 ns tr tf Minimum Input Rise and Fall Time 20V 1000 1000 1000 ns 45V 500 500 500 ns 60V 400 400 400 ns CPD Power Dissipation (per package) pF Capacitance (Note 5) CIN Maximum Input Capacitance 5 10 10 10 pF Note 5 CPD determines the no load dynamic power consumption PDeCPD VCC2 faICC VCC and the no load dynamic current consumption ISeCPD VCC faICC 3 |
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