DA9213-A datasheet(5/62 Pages) DIALOG

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DA9213-A and DA9214-A

Auto Grade Multi-Phase 5A/Phase Buck Converter

Datasheet

Revision 1.4

08-May-2017

CFR0011-120-00

5 of 62

Figures

Figure 1: DA9213-A System Diagram ................................................................................................... 2

Figure 2: DA9214-A System Diagram ................................................................................................... 2

Figure 3: Connection Diagram .............................................................................................................. 7

Figure 4: 66 VFBGA Power Derating Curve........................................................................................ 11

Figure 5: 2-WIRE Bus Timing.............................................................................................................. 16

Figure 6: 4-WIRE Bus Timing.............................................................................................................. 17

Figure 7: DA9213-A Efficiency vs Load, VOUT = 1.0 V, 0-20 A ......................................................... 18

Figure 8: DA9213-A Efficiency vs Load, VIN = 3.6 V, 0-20 A ............................................................. 18

Figure 9: DA9214-A Efficiency vs Load, VOUT = 1.0 V, 0-10 A ......................................................... 19

Figure 10: DA9214-A Efficiency vs Load, VIN = 3.6 V, 0-10 A ........................................................... 19

Figure 11: Interface of DA9213-A/14-A with DA9063 and the Host Processor................................... 20

Figure 12: Typical Application of DA9213-A........................................................................................ 21

Figure 13: Typical Application of DA9214-A........................................................................................ 22

Figure

14: Concept of Control of the Buck’s Output Voltage .............................................................. 25

Figure 15: Resistive Divider from VOUT to FBAN .............................................................................. 26

Figure 16: GPIO Principle of Operation (example paths).................................................................... 29

Figure 17: Schematic of 4-WIRE and 2-WIRE Power Manager Bus .................................................. 31

Figure 18: 4-WIRE Host Write and

Read Timing (nCS_POL = ‘0’, CPOL = ‘0’, CPHA = ‘0’) ............. 32

Figure 19: 4-

WIRE Host Write and Read Timing (nCS_POL= ‘0’, CPOL = ‘0’, CPHA = ‘1’) .............. 33

Figure 20: 4-

WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘0’) ............. 33

Figure 21: 4-

WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘1’) ............. 34

Figure 22: Timing of 2-WIRE START and STOP Condition ................................................................ 36

Figure 23: 2-WIRE Byte Write (SDA Line) .......................................................................................... 37

Figure 24: Examples of 2-WIRE Byte Read (SDA Line) ..................................................................... 37

Figure 25: Examples of 2-WIRE Page Read (SDA Line) .................................................................... 37

Figure 26: 2-WIRE Page Write (SDA Line) ......................................................................................... 38

Figure 27: 2-WIRE Repeated Write (SDA Line) .................................................................................. 38

Figure 28: DA9213-A/14-A VFBGA Package Outline Drawing ........................................................... 59

Tables

Table 1: Pin Description ........................................................................................................................ 8

Table 2: Pin Type Definition .................................................................................................................. 9

Table 3: Absolute Maximum Ratings................................................................................................... 10

Table 4: Recommended Operating Conditions ................................................................................... 10

Table 5: Buck Converters Characteristics ........................................................................................... 11

Table 6: IC Performance and Supervision .......................................................................................... 14

Table 7: Digital I/O Characteristics ...................................................................................................... 14

Table 8: 2-WIRE Control Bus Characteristics ..................................................................................... 15

Table 9: 4-WIRE Control Bus Characteristics ..................................................................................... 17

Table 10: 4-WIRE Clock Configurations.............................................................................................. 31

Table 11: 4-WIRE Interface Summary ................................................................................................ 35

Table 12: Over-Temperature Thresholds ............................................................................................ 39

Table 13: Register Map ....................................................................................................................... 41

Table 14: Recommended Capacitor Types......................................................................................... 57

Table 15: Recommended Inductor Types ........................................................................................... 58

Table 16: Ordering Information ........................................................................................................... 60

DA9213-A Datasheet(PDF) 5 Page - Dialog Semiconductor

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