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CBTS3306 Datasheet(PDF) 2 Page - NXP Semiconductors |
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CBTS3306 Datasheet(HTML) 2 Page - NXP Semiconductors |
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2 / 8 page ![]() Philips Semiconductors Product data CBTS3306 Dual bus switch with Schottky diode clamping 2 2001 Nov 08 853-2306 27313 FEATURES • 5 Ω switch connection between two ports • TTL-compatible input levels • Package options include plastic small outline (SO) and thin shrink small outline (TSSOP) • Latch-up protection exceeds 100 mA per JESD78 • ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101 DESCRIPTION The CBTS3306 Dual FET Bus Switch features independent line switches with Schottky diodes on the I/OS to clamp undershoot. Each switch is disabled with the associated Output Enable (OE) input is high. The CBTS3306 is characterized for operation from –40 to +85 °C. PIN CONFIGURATION 1 2 3 45 6 7 8 1OE 1A 1B GND VCC 2OE 2B 2A SA00535 PIN DESCRIPTION PIN NUMBER SYMBOL NAME AND FUNCTION 1, 7 1OE, 2OE Output enable 2, 5 1A, 2A A port inputs 3, 6 1B, 2B B port outputs 4 GND Ground (0 V) 8 VCC Positive supply voltage QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Tamb = 25 °C; GND = 0 V TYPICAL UNIT tPLH tPHL Propagation delay A to B or B to A CL = 50 pF; VCC = +5.0 V ±0.5 V 0.25 (MAX) ns CIO(OFF) Port off capacitance VO = 3 V or 0; OE = VCC 7.60 pF ICC Quiescent supply current VCC = 5.5 V; IO = 0, VI = VCC or GND 3 µA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE DWG NUMBER 8-pin plastic SO –40 to 85 °C CBTS3306D SOT96-1 8-pin plastic TSSOP –40 to 85 °C CBTS3306PW SOT530-1 Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging. LOGIC DIAGRAM (positive logic) 2 1A 3 1B SA00618 1 1OE 5 2A 6 2B 1 2OE FUNCTION TABLE INPUT FUNCTION OE FUNCTION L A port = B port H Disconnect |
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