UR5596G-SH2-R datasheet(6/11 Pages) UTC

6 / 11 page

UR5596

CMOS IC

UNISONIC TECHNOLOGIES CO., LTD

6 of 11

www.unisonic.com.tw

QW-R502-045.D



T Y PI CAL APPLI CAT I ON CI RCU I T S

Following demonstrate several different application circuits to illustrate some of the options that are possible in

configuring the UTC UR5596. The individual circuit performance can be found in the Typical Performance

Characteristics that curve graphs illustrate how the maximum output current is affected by changes in AVIN and PVIN.

STUB-SERIES TERMINATED LOGIC(SSTL) TERMINATION SCHEME

SSTL was created to improve signal integrity of the data transmission across the memory bus. This termination

scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered

with DDR-SDRAM. Class II single parallel termination(SSTL-2) is the most popular termination form. It involves one

RS series resistor from the chipset to the memory and one RT termination resistor (refer to Figure 1). RS and RT are

changeable to meet the current requirement from UR5596, the recommended values both RS and RT are 25Ω.

Figure 1. SSTL-Termination Scheme

FOR SSTL-2 APPLICATIONS

For the majority of applications that implement the SSTL- 2 termination scheme, it is recommended to connect all

the input rails to the 2.5V rail as Figure 2. This provides an optimal trade-off between power dissipation and

component count and selection.

DDQ

SENSE

REF

GND

SHDN

AVIN

PVIN

CIN

SHDN

VDDQ=2.5V

VDD=2.5V

COUT

CREF

VREF=1.25V

VTT=1.25V

UTC UR5596

Figure 2. Recommended SSTL-2 Implementation

UR5596G-SH2-R Datasheet(PDF) 6 Page - Unisonic Technologies