ACT81460 datasheet(32/60 Pages) ACTIVE-SEMI

32 / 60 page

ACT81460

Rev 1.0, 18-Dec-2018

Innovative PowerTM

www.active-semi.com

ActiveSwitcherTM is a trademark of Active-Semi

by default used for this function. Connect a pull-up

resistor from the nIRQ pin to an appropriate voltage

supply (typically VSYS or VIO_IN). nIRQ is typically

used to drive the interrupt input of the system processor.

Many of the ACT81460's functions support interrupt-

generation. These are typically masked by default to

block unnecessary interrupts but may be unmasked via

the I2C interface per the user’s choice through firmware.

In general every output can generate interrupts due to

current limits, UV or OV conditions. GPIOs can also be

configured to generate interrupts when the GPIO is

configured as a digital input. Push button function,

manual reset, input UV/OV, thermal shutdown and other

such functions can also trigger interrupts and these are

available in the register map of the master control core,

also referred to as the master tile. Examples of

conditions that can cause nIRQ to trigger are:

1. Die temperature warning generated

2. Any buck regulator exceeding peak current limit for

8 cycles after soft start or a UV/OV condition.

3. Any LDO regulator exceeding current limit for more

than 20uS after soft start or a UV/OV condition.

4. Input goes above OVP threshold or falls below the

UV threshold.

5. Watch Dog timer expiring.

6. Push Button status when the nPBIN pin is asserted.

The PB status register bit and PB counter register

can then be used to check the PB time and take

appropriate action.

If any of the faults occur and the nIRQ output is enabled,

the nIRQ pin will be driven low. Following the nIRQ pin

being asserted, a read operation of the interrupt causing

status bit will clear the interrupt, so the interrupt is

cleared upon reading provided the interrupt causing

condition is removed.

nRESET

The ACT81460 provides a reset function to issue a

master reset to the system CPU/controller. nRESET is

immediately asserted low when either the VIN voltage

is above or below the UV or OV thresholds or any power

supply that is connected to the nRESET functionality

goes below its Power Good threshold. The IC’s specific

CMI configures which power supplies are connected to

the nRESET functionality. After startup, nRESET de-as-

serts after a programmable delay time when VIN and all

connected power supply outputs are above their re-

spective UVLO thresholds. The reset delay time, 20ms

to 100ms, is controlled by the I2C TRST_DLY register

bits. The IC’s CMI programs the specific GPIOx pin

used for the reset functionality. The CMI also programs

which regulators outputs are monitored for the reset

functionality.

Output Under/Over Voltage

The ACT81460 monitors the output voltages for under

voltage and over voltage conditions. If an output enters

an UV/OV fault condition, the IC asserts IRQ and

nRESET and shuts down all outputs for 100ms and then

restarts with the programmed power up sequence. If an

output is in current limit, it is possible that its voltage can

drop below the UV threshold which also shuts down all

outputs. If this behavior is not desired, mask the

appropriate fault bit. If the fault is masked, the fault

status bit shows the real-time fault status. Note that the

IC’s specific CMI sets the defaults for which regulators

mask the UV and OV fault conditions.

Output Current Limit

The ACT81460 incorporates overcurrent for all

converters and load switches. Refer to each section for

the details.

Thermal Warning and Thermal Shutdown

The ACT81460 monitors its internal die temperature

and reports a warning via nIRQ when the temperature

rises above the Thermal Warning Threshold of typically

125 deg C. It shuts down all outputs when the tempera-

ture increases above 155 deg C. The Thermal Warning

can be masked via I2C. The temperature warning and

fault flags still provide real-time status even if the faults

are masked. Masking just prevents the faults from being

reported via the nIRQ pin.

The IC includes a Thermal Low Power mode. When the

die temperature goes above 70°C, the IC places a

100kΩ resistor on the output of the LDOs to ground.

This prevents the output voltages from increasing due

to leakage through the internal FETs.

Sequencing

The ACT81460 provides the end user with extremely

versatile sequencing capability that can be optimized for

many different applications. Each output has four basic

sequencing parameters: input trigger, turn-on delay,

turn-off delay, and output voltage. Each of these

parameters is controlled via the ICs internal registers.

The specifics for this IC as well as others are detailed at

the end of the datasheet. Contact sales@active-

semi.com for custom sequencing configurations. Refer

the

Active-Semi

Application

Note

AN116,

ACT81460VM101 Register Definitions, for full details on

the I2C register map functionality and programming

ranges.

Input trigger. The input trigger for a regulator is the

event that turns that regulator on. Each output can have

a separate input trigger. The input trigger can be the

ACT81460 Datasheet(PDF) 32 Page - Active-Semi, Inc

ACT81460 Datasheet(HTML) 32 Page - Active-Semi, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL