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CDB6403 Datasheet(PDF) 21 Page - Cirrus Logic

Part # CDB6403
Description  Echo-Cancelling Codec
PDF  54 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CDB6403 Datasheet(HTML) 21 Page - Cirrus Logic

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Register SSI_CR1
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
CB
AGCD
res
res
CAL
GADCI
res
res
NCC
HDD
SD
ACC
00
00
00
00
00
00
This register is read/written by the CPU every sample time. This register is cleared at Reset by the SSI.
BIT
NAME
VALUE
FUNCTION
CB
Codec Bypass
0
R
1
Normal operation.
Codec is bypassed by the CPU to facilitate test.
AGCD
AGC Disable
0
R
1
Normal operation.
AGC is disabled. Will affect volume control.
res
Reserved for test
0
R
Must be 0.
res
Reserved for test
0
R
Must be 0.
CAL
Codec Analog Loopback
0
R
1
Normal operation.
Connect ADC to DAC internally.
GADCI
Ground ADC Input
0
R
1
Normal operation.
ADC input is grounded to facilitate test.
res
Reserved for test
0
R
Must be 0.
res
Reserved for test
0
R
Must be 0.
NCC
NEC Coefficient Clear
0
R
1
Normal operation.
The network canceller coefficients are cleared.
HDD
Half-Duplex Disable
0
R
1
Normal operation.
Half-duplex mode, which is normally used during
convergence, is disabled.
SD
Suppression Disable
0
R
1
Normal operation.
Supplementary suppression in the transmit path,
which normally operates in conjunction with the
echo cancellers, is disabled.
ACC
AEC Coefficient Clear
0
R
1
Normal operation.
The acoustic canceller coefficients are cleared.
"R" indicates value after Reset
CS6403
DS192PP6
21



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