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SAA32M4 Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers

Part # SAA32M4
Description  DOUBLE DATA RATE (DDR) SDRAM
PDF  13 Pages
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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SAA32M4 Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers

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128Mb: x4, x8, x16
DDR SDRAM
PDF: 09005aef80505d1b / Source: 09005aef80469e44
128Mb: x4, x8, x16 DDR SDRAM
Rev: 11/23/2004
7
www.spectek.com
SpecTek reserves the right to change products or specifications
without notice.
© 2001, 2002, 2004 SpecTek
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(25°C < TA < +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)
AC CHARACTERISTICS
-75
-8
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
NOTES
Access window of DQs from CK/CK#
tAC
-0.75
+0.75
-0.8
+0.8
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
30
CK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
30
CL = 2.5
tCK (2.5)
7.5
12
10
12
ns
52
Clock cycle time
DQ and DM input hold time relative to DQS
tDH
0.5
0.6
ns
26, 31
DQ and DM input setup time relative to DQS
tDS
0.5
0.6
ns
26, 31
DQ and DM input pulse width (for each input)
tDIPW
1.75
2
ns
31
Access window of DQS from CK/CK#
tDQSCK
-0.75
+0.75
-0.8
+0.8
ns
DQS input high pulse width
tDQSH
0.35
0.35
tCK
DQS input low pulse width
tDQSL
0.35
0.35
tCK
DQS-DQ skew, DQS to last DQ valid, per group, per
access
tDQSQ
0.5
0.6
ns
25, 26
DQS-DQ skew, first DQS to last DQ valid, per access
tDQSQA
0.7
0.8
ns
36
Write command to first DQS latching transition
tDQSS
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK rising – setup time
tDSS
0.2
0.2
tCK
DQS falling edge from CK rising – hold time
tDSH
0.2
0.2
tCK
Half clock period
tHP
tCH,
tCL
tCH,
tCL
ns
34
Data-out high-impedance window from CK/CK#
tHZ
-0.75
+0.75
-0.8
+0.8
ns
18
Data-out low-impedance window from CK/CK#
tLZ
-0.75
+0.75
-0.8
+0.8
ns
18
Address and control input hold time (fast slew rate)
tIH
f
.90
1.1
ns
14
Address and control input setup time (fast slew rate)
tIS
f
.90
1.1
ns
14
Address and control input hold time (slow slew rate)
tIH
s
1
1.1
ns
14
Address and control input setup time (slow slew rate)
tIS
s
1
1.1
ns
14
LOAD MODE REGISTER command cycle time
tMRD
15
16
ns
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
tQH
tHP -
tQHS
tHP -
tQHS
ns
25, 26
Data hold skew factor
tQHS
0.75
1
ns
ACTIVE to PRECHARGE command
tRAS
45
16,000
50
16,000
ns
35
ACTIVE to READ with Auto precharge command
tRAP
ns
46
ACTIVE to ACTIVE/AUTO REFRESH command
period
tRC
65
70
ns
AUTO REFRESH command period
tRFC
75
80
ns
50
ACTIVE to READ or WRITE delay
tRCD
20
20
ns
PRECHARGE command period
tRP
20
20
ns
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
42
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
ACTIVE bank
a to ACTIVE bank b command
tRRD
15
15
ns



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