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74LS195 Datasheet(PDF) 2 Page - ON Semiconductor

Part # 74LS195
Description  LOW POWER SCHOTTKY
PDF  8 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

74LS195 Datasheet(HTML) 2 Page - ON Semiconductor

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SN74LS195A
http://onsemi.com
2
CONNECTION DIAGRAM DIP (TOP VIEW)
Parallel Enable (Active LOW) Input
Parallel Data Inputs
First Stage J (Active HIGH) Input
First Stage K (Active LOW) Input
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Parallel Outputs
Complementary Last Stage Output
PE
P0 – P3
J
K
CP
MR
Q0 – Q3
Q3
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
mA HIGH/1.6 mA LOW.
HIGH
LOW
(Note a)
LOADING
PIN NAMES
LOGIC SYMBOL
2
10
3
45
6
7
11
12
13
14
15
1
9
J
PE
CP
K
MR
P0 P1 P2 P3
Q0 Q1 Q2 Q3
Q3
VCC = PIN 16
GND = PIN 8
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
14
13
12
11
10
9
1234
5
6
7
16
15
8
VCC
MR
Q0
Q1
Q2
Q3
CP
Q3
PE
JK
P0
P1
P2
P3
GND



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