9DB306BL

www.icst.com/products/hiperclocks.html

REV. A APRIL 7, 2005

5

Integrated

Circuit

Systems, Inc.

ICS9DB306

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

1k

10k

100k

1M

10M

100M

100MHz

RMS Phase Jitter (Random)

1.5MHz to 22MHz = 3ps (typical)

Phase Noise Result by adding

PCI Express™ Filter to raw data

PCI Express™ Filter

The illustrated phase noise plot was taken using a low phase

noise signal generator, the noise floor of the signal generator is

less than that of the device under test.

Using this configuration allows one to see the true spectral pu-

rity or phase noise performance of the PLL in the device under

test. Due to the tracking ability of a PLL, it will track the input

signal up to its loop bandwidth.Therefore, if the input phase noise

is greater than that of the VCO, it will increase the output phase

noise performance of the device. It is recommended that the

phase noise performance of the input is verified in order to

achieve the above phase noise performance.

Raw Phase Noise Data