PS4210-1099
Page 1 of 30
Advanced Hardware Architectures, Inc.
1.0
INTRODUCTION
The AHA4210, referred to as the RSVP, is a
single-chip Forward Error Correction LSI device
combining a Viterbi decoder, a Reed-Solomon
decoder, a descrambler (energy dispersal) and a
deinterleaver. The device conforms to the MPEG-II
transport layer protocol specified by ISO/IEC
standard and FEC requirements of Digital Video
Broadcasting (DVB) DT/8622/DVB and DT/8610/
III-B specification. These documents are referred to
as the DVB specification.
The Viterbi decoder supports selectable code
rates of 1/2, 2/3, 3/4, 5/6, 6/7 or 7/8 using industry
standard puncturing algorithms. Viterbi decoded
data rate is up to 62 Mbits/second at all code rates.
The chip also performs byte alignment and block/
packet synchronization detecting sync bytes used in
transmission. The descrambling function is
selectable with a programmable seed or performed
externally. Each functional block may be bypassed
giving more flexibility to a system designer.
Block size programmability, several code rate
choices and programmable RS error correction
capability allows flexibility to a digital
communications system designer incorporating
Forward Error Correction into a receiver. Intel
80C188 multiplexed parallel or serial I2C protocol
interface allows the system microprocessor to
program internal registers and monitor channel
performance.
This document contains key features,
correction terms, functional description, signal
functions, Related Technical Publications, DC and
AC characteristics, pinout, package dimension and
ordering information.
1.1
APPLICATIONS
• Satellite communications/VSAT
• DBS
• Military Communications
1.2
FEATURES
GENERAL:
• Conforms to the ISO/IEC-CD 13818-1 MPEG-II
transport layer protocol and Digital Video
Broadcasting (DVB)FEC specification
• Viterbi decoded data rates up to 62 Mbits/sec at
any code rate
• Programmable block size from 34 to 255 bytes
• Multiplexed parallel Intel 80C188 or serial I2C
protocol microprocessor interface
• Byte or serial data output
• On-Chip error rate monitor
• Programmable bypass modes for each of the
major blocks
• Configured to DVB mode of operation on
power-up
• 68 pin PLCC
VITERBI DECODER:
• Selectable decoder rates 1/2, 2/3, 3/4, 5/6, 6/7
and 7/8 or automatic acquire mode
• 3-Bit soft-decision decoder inputs
• Constraint length k=7
SYNCHRONIZATION CONTROL:
• Automatic synchronization capability for QPSK
based demodulator
• Up to one sync byte per block
• Responds to inverted sync byte
REED-SOLOMON:
• t=1 through 8 in increments of 0.5
• Correction capability of up to 8 bytes
• Internal FIFOs
DEINTERLEAVER:
• Programmable convolutional deinterleaving
(Ramsey II, Ramsey II modified or Forney) to
depth I=16
• No external RAM required
ENERGY DISPERSAL:
• Selectable on-chip DVB specification Energy
Dispersal
• Optional bypass mode
• Programmable seed
1.3
CONVENTIONS AND NOTATIONS
- Certain signals are logically true at a voltage
defined as “low” in the data sheet. All such
signals have an “N” appended to the end of the
signal name. For example, RSTN and RDYON.
- “Signal assertion” means the signal is logically true.
- Hex values are defined with a prefix of “0x”,
such as “0x10”.
- A range of signal names is denoted by a set of
colons between the numbers. Most significant bit
is always shown first, followed by least
significant bit. For example, ERRSTAT[6:0]
represents number of bytes corrected by the
Reed-Solomon decoder.
- A product of two variables is expressed with an
“x”, for example, BLKLEN2 x JDEPTH
represents Block Length multiplied by Interleave
Depth.
- Megabytes per second is referred to as MBytes/
sec or MB/sec. Megabits per second is referred as
Mbits/sec or Mb/sec.
- Frequency of a clock signal is referred to as
F(name). For example, F(VCLK) specifies
frequency of VCLK.
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