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AM6548BACDXEAF Datasheet(PDF) 166 Page - Texas Instruments |
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AM6548BACDXEAF Datasheet(HTML) 166 Page - Texas Instruments |
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166 / 282 page  Table 7-27. CPSW2G MDIO Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.9 3.6 V/ns OUTPUT CONDITIONS CL Output load capacitance 10 470 pF Table 7-28. Timing Requirements for MDIO Input NO. PARAMETER MIN MAX UNIT MDIO1 tsu(MDIO_MDC) Setup time, MDIO_MDIO valid before MDIO_MDC high 90 ns MDIO2 th(MDIO_MDC) Hold time, MDIO_MDIO valid after MDIO_MDC high 0 ns Table 7-29. Switching Characteristics Over Recommended Operating Conditions for MDIO Output NO. PARAMETER MIN MAX UNIT MDIO3 tc(MDC) Cycle time, MDIO_MDC 400 ns MDIO4 tw(MDCH) Pulse Duration, MDIO_MDC high 160 ns MDIO5 tw(MDCL) Pulse Duration, MDIO_MDC low 160 ns MDIO7 td(MDC_MDIO) Delay time, MDIO_MDC low to MDIO_MDIO valid -150 150 ns MDIO3 MDIO1 MDIO2 MDIO7 MDIO4 MDIO5 MDIO[x]_MDC MDIO[x]_MDIO (input) MDIO[x]_MDIO (output) CPSW2G_MDIO_TIMING_01 Figure 7-32. CPSW2G MDIO Diagrams Receive and Transmit 7.9.5.2.2 CPSW2G RMII Timings Section 7.9.5.2.2.1, Section 7.9.5.2.2.2, Figure 7-33, and Figure 7-34 present timing requirements for CPSW2G RMII receive. Table 7-30 presents timing conditions for CPSW2G RMII. Table 7-30. CPSW2G RMII Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.9 3.6 V/ns OUTPUT CONDITIONS CL Output load capacitance 3 25 pF 7.9.5.2.2.1 Timing Requirements for RMII[x]_REFCLK - RMII Mode NO. PARAMETER DESCRIPTION MIN TYP MAX UNIT RMII1 tc(REF_CLK) Cycle time, REF_CLK 19.999 20.001 ns AM6548, AM6528, AM6526 SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021 www.ti.com 166 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AM6548 AM6528 AM6526 |
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