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AM6548BACDXEAF Datasheet(PDF) 168 Page - Texas Instruments |
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AM6548BACDXEAF Datasheet(HTML) 168 Page - Texas Instruments |
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168 / 282 page  7.9.5.2.3 CPSW2G RGMII Timings Section 7.9.5.2.3.1, Section 7.9.5.2.3.2, and Figure 7-36 present timing requirements for receive RGMII operation. Table 7-31 presents timing conditions for CPSW2G RGMII. Table 7-31. CPSW2G RGMII Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 2.64 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 20 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Mismatch Delay) Propagation delay mismatch across all traces RGMII[x]_RXC, RGMII[x]_RD[3: 0], RGMII[x]_RX_C TL 50 ps RGMII[x]_TXC, RGMII[x]_TD[3: 0], RGMII[x]_TX_C TL 50 ps 7.9.5.2.3.1 Timing Requirements for RGMII[x]_RCLK - RGMII Mode NO. PARAMETER DESCRIPTION MODE MIN TYP MAX UNIT RGMII1 tc(RXC) Cycle time, RXC 10Mbps 360 440 ns 100Mbps 36 44 ns 1000Mbps 7.2 8.8 ns RGMII2 tw(RXCH) Pulse duration, RXC high 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns RGMII3 tw(RXCL) Pulse duration, RXC low 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns 7.9.5.2.3.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode NO. PARAMETER DESCRIPTION MODE MIN TYP MAX UNIT RGMII4 tsu(RD-RXC) Setup time, RD[3:0] valid before RXC high/low 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns tsu(RX_CTL-RXC) Setup time, RX_CTL valid before RXC high/low 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns AM6548, AM6528, AM6526 SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021 www.ti.com 168 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AM6548 AM6528 AM6526 |
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