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AM6548BACDXEAF Datasheet(PDF) 172 Page - Texas Instruments |
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AM6548BACDXEAF Datasheet(HTML) 172 Page - Texas Instruments |
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172 / 282 page  7.9.5.5 DSS For more details about features and additional description information on the device Display Subsystem – Video Output Ports, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description. Table 7-33, Table 7-34, Figure 7-39 and Figure 7-40 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 7-33. DPI Video Output Switching Characteristics NO. PARAMETER MIN MAX UNIT D1 tc(VOUT1_PCLK) Cycle time, VOUT1_PCLK 6.06 ns D2 tw(VOUT1_PCLKL) Pulse duration, VOUT1_PCLK low 0.475 * P(1) ns D3 tw(VOUT1_PCLKH) Pulse duration, VOUT1_PCLK high 0.475 * P(1) ns D4 td(VOUT1_PCLK- VOUT_DATA) Delay time, VOUT1_PCLK to VOUT1_DATA[23:0] -0.68 1.78 ns D5 td(VOUT1_PCLK- VOUT_CTRL) Delay time, VOUT1_PCLK to VOUT1_VSYNC, VOUT1_HSYNC, VOUT1_DE -0.68 1.78 ns (1) P = output VOUT1_PCLK period in ns. VOUT1_PCLK VOUT1_VSYNC VOUT1_HSYNC VOUT1_DATA[23:0] VOUT1_DE data_1 data_2 data_n D1 D2 D3 D5 D5 D4 D5 DPI_01 VOUT1_PCLK Falling-edge Clock Reference Rising-edge Clock Reference A. The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock. B. The polarity and the pulse width of VOUT1_HSYNC and VOUT1_VSYNC are programmable, refer to section Display Subsystem (DSS) in the device TRM. C. The VOUT1_PCLK frequency can be configured, refer to section Display Subsystem (DSS) in the device TRM. Figure 7-39. DPI Video Output AM6548, AM6528, AM6526 SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021 www.ti.com 172 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AM6548 AM6528 AM6526 |
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