AM6548BACDXEAF datasheet(173/282 Pages) TI

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Table 7-34. DPI External Pixel Clock Input Timing Requirements

NO.

MIN

MAX UNIT

tc(VOUT1_EXTPCLKIN)

Cycle time, VOUT1_EXTPCLKIN

6.06

tw(VOUT1_EXTPCLKIN)

Pulse duration, VOUT1_EXTPCLKIN low

0.475 * P(1)

tw(VOUT1_EXTPCLKIN)

Pulse duration, VOUT1_EXTPCLKIN high

0.475 * P(1)

(1)

P = output VOUT1_PCLK period in ns.

VOUT1_EXTPCLKIN

DPI_02

Falling-edge Clock Reference

Rising-edge Clock Reference

VOUT1_EXTPCLKIN

Figure 7-40. DPI External Pixel Clock Input

For more information, see section Display Subsystem (DSS) in the device TRM.

7.9.5.6 eCAP

The supported features by the device eCAP are:

• 32-bit time base counter

• 4-event time-stamp registers (each 32 bits)

• Independent edge polarity selection for up to four sequenced time-stamp capture events

• Interrupt capabilities on any of the four capture events

• Input capture signal pre-scaling (from 1 to 16)

• Support of different capture modes (single shot capture, continuous mode capture, absolute timestamp

capture or difference mode time-stamp capture)

Table 7-35 represents eCAP timing conditions.

Table 7-35. eCAP Timing Conditionns

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

V/ns

OUTPUT CONDITIONS

Output load capacitance

Section 7.9.5.6.1 and Section 7.9.5.6.2 present timing and switching characteristics for eCAP (see Figure 7-41

and Figure 7-42).

7.9.5.6.1 eCAP Timing Requirements

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

CAP1

tw(CAP)

Pulse duration, CAP (asynchronous)

3 + 2P

(1)

P = sysclk period in ns.

CAP

CAP1

EPERIPHERALS_TIMNG_01

Figure 7-41. eCAP Timing Requirements

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AM6548, AM6528, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

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