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AM6548BACDXEAF Datasheet(PDF) 178 Page - Texas Instruments

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Part # AM6548BACDXEAF
Description  AM654x, AM652x Sitara??Processors Silicon Revision 2.1
PDF  282 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM6548BACDXEAF Datasheet(HTML) 178 Page - Texas Instruments

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7.9.5.9.2 GPIO Switching Characteristics
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
GP1
tw(GPIO_OUT)
Minimum Output Pulse Width
-4.6 +
0.975P(1)
ns
(1)
P = functional clock period in ns.
For more information, see section General-Purpose Interface (GPIO) in the device TRM.
7.9.5.10 GPMC
For more details about features and additional description information on the device General-Purpose Memory
Controller, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed
Description.
Table 7-39 presents the timing conditions for GPMC.
Table 7-39. GPMC Timing Conditions
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
Input Conditions
SRI
Input slew rate
1.65
4
V/ns
Output Conditions
CL
Output load capacitance
5
20
pF
7.9.5.10.1 GPMC and NOR Flash—Synchronous Mode
Section 7.9.5.10.1.1 and Section 7.9.5.10.1.2 assume testing over the recommended operating conditions and
electrical characteristic conditions below (see Figure 7-48 through Figure 7-52).
7.9.5.10.1.1 GPMC and NOR Flash Timing Requirements—Synchronous Mode
NO.
PARAMETER
DESCRIPTION
MODE(2)
MIN
MAX UNIT
F12
tsu(dV-clkH)
Setup time, input data GPMC_AD[15:0] valid
before output clock GPMC_CLK high
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
2.17
ns
not_div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
3.46
ns
F13
th(clkH-dV)
Hold time, input data GPMC_AD[15:0] valid after
output clock GPMC_CLK high
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
1.78
ns
not_div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
1.78
ns
F21
tsu(waitV-clkH)
Setup time, input wait GPMC_WAIT[x] valid before
output clock GPMC_CLK high (1)
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
2.17
ns
not_div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
3.46
ns
F22
th(clkH-waitV)
Hold time, input wait GPMC_WAIT[x] valid after
output clock GPMC_CLK high (1)
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
1.78
ns
not_div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
1.78
ns
(1)
In GPMC_WAIT[x], x is equal to 0 or 1.
(2)
For div_by_1_mode:
AM6548, AM6528, AM6526
SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021
www.ti.com
178
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: AM6548 AM6528 AM6526



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