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AM6548BACDXEAF Datasheet(PDF) 240 Page - Texas Instruments |
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AM6548BACDXEAF Datasheet(HTML) 240 Page - Texas Instruments |
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240 / 282 page  NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRRG10 tw(TXCL) Pulse duration, TXC low 10 Mbps 160 240 ns 100 Mbps 16 24 ns 1000 Mbps 3.6 4.4 ns SPRS91x_TIMING_PRU_RGMII_RT_06 RGMII_TXC PRRG9 PRRG10 PRRG8 PRRG11 PRRG11 Figure 7-116. PRU_ICSSG RGMII_TXC Switching Characteristics 7.9.5.21.6.2.4 PRU_ICSSG RGMII Switching Characteristics - RGMII_TD[3:0] and RGMII_TX_CTL NO. PARAMETER DESCRIPTION MODE MIN TYP MAX UNIT PRRG12 tosu(TD-TXC) Output setup time, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC high/low 10 Mbps 100 Mbps 1.2 ns 1000 Mbps 1.05 (1) ns tosu(TX_CTL-TXC) Output setup time, RGMII[x]_TX_CTL valid to RGMII[x]_TXC high/low 10 Mbps 100 Mbps 1.2 ns 1000 Mbps 1.05 (1) ns PRRG13 toh(TD-TXC) Output hold time, RGMII[x]_TD[3:0] valid after RGMII[x]_TXC high/low 10 Mbps 100 Mbps 1.2 ns 1000 Mbps 1.05 (1) ns toh(TX_CTL-TXC) Output hold time, RGMII[x]_TX_CTL valid after RGMII[x]_TXC high/low 10 Mbps 100 Mbps 1.2 ns 1000 Mbps 1.05 (1) ns (1) 1000Mbps operation requires that the 4 data pins (RGMII[x]_TD[3:0]) and RGMII[x]_TX_CTL have their board propagation delays matched to within 50 ps of RGMII[x]_TXC. A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled. B. Data and control information is received using both edges of the clocks. RGMII_TD[3:0] carries data bits 3-0 on the rising edge of RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TX_CTL carries TXDV on rising edge of RGMII_TXC and RTXERR on falling edge of RGMII_TXC. Figure 7-117. PRU_ICSSG Transmit Interface Timing RGMII Mode AM6548, AM6528, AM6526 SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021 www.ti.com 240 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AM6548 AM6528 AM6526 |
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