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AM6548BACDXEAF Datasheet(PDF) 241 Page - Texas Instruments |
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AM6548BACDXEAF Datasheet(HTML) 241 Page - Texas Instruments |
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241 / 282 page  7.9.5.21.6.3 PRU_ICSSG MII_RT Electrical Data and Timing Note The PRU_ICSSG are contains a second layer of multiplexing to enable additional functionality (including MII functionality) on the PRU GPO and GPI signals. This internal wrapper multiplexing is described in the Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem - Gigabit (PRU_ICSSG) section in Peripherals chapter in the device TRM. Note In order to ensure the MII_G_RT I/O timing values published in the device data sheet, the PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 2) core clock must be configured for 200 MHz, 225 MHz, or 250 MHz and the TX_CLK_DELAYn (where n = 0 or 1) bit field in the ICSSG_TXCFG0/1 register must be set to 0h (default value). Table 7-77 presents PRU_ICSSG MII timing conditions. Table 7-77. PRU_ICSSG MII Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.9 3.6 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 20 pF 7.9.5.21.6.3.1 PRU_ICSSG MII_RT Timing Requirements – MII_RX_CLK NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PMIR1 tc(RX_CLK) Cycle time, RX_CLK 10 Mbps 399.96 400.04 ns 100 Mbps 39.996 40.004 ns PMIR2 tw(RX_CLKH) Pulse Duration, RX_CLK High 10 Mbps 140 260 ns 100 Mbps 14 26 ns PMIR3 tw(RX_CLKL) Pulse Duration, RX_CLK Low 10 Mbps 140 260 ns 100 Mbps 14 26 ns MII_RXCLK PMIR2 PMIR3 PMIR1 SPRS91x_TIMING_PRU_MII_RT_04 Figure 7-118. PRU_ICSSG MII_RXCLK Timing www.ti.com AM6548, AM6528, AM6526 SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 241 Product Folder Links: AM6548 AM6528 AM6526 |
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