PJ3844B / PJ3845B
High Performance Current Mode Controller
7-14
2004/11. Rev B
FIGURE 17-REPRESENTATIVE BLOCK DIAGRAM
Pin numbers adjacent to terminals are for the 8 pin dual-in-line package.
Pin numbers in parenthesis are for the SOP-14 package.
FIGURE 18-TIMING DIAGRAM
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functional before
the output stage is enabled. The positive power supply
terminal (VCC) and the reference output (Vref) are each
monitored by separate comparators.Each has built-in
hysteresis to prevent erratic output behavior as their respective
thresholds are crossed.The VCC comparator upper and lower
thresholds are 1 8.4 V/7.6 V for the UC3845A
The Vref comparator upper and lower thresholds are
3.6V/3.4V.The large hysteresis and low start-up current of the
UC3844B makes it ideally suited in off-line converter
applications where efficient bootstrap start-up technique
(Figure 33). 36 V zener is connected as a shunt regulator from
VCC to ground.Its purpose is to protect the IC from excessive
voltage that can occur during system start-up. The minimum
operating voltage for the UC3844B is 11V.
UNDERVOLTAGE LOCKOUT
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