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LQFP64 Datasheet(PDF) 161 Page - STMicroelectronics

Part # LQFP64
Description  Arm® Cortex®-M4 32b MCUFPU, 210DMIPS, up to 1MB Flash/1924KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
PDF  204 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

LQFP64 Datasheet(HTML) 161 Page - STMicroelectronics

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DS8626 Rev 9
161/203
STM32F405xx, STM32F407xx
Electrical characteristics
5.3.27
Camera interface (DCMI) timing specifications
Unless otherwise specified, the parameters given in Table 87 for DCMI are derived from
tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 13, with the following configuration:
•
PCK polarity: falling
•
VSYNC and HSYNC polarity: high
•
Data format: 14 bits
Figure 72. DCMI timing diagram
Table 86. Switching characteristics for NAND Flash write cycles(1)
1. CL = 30 pF.
Symbol
Parameter
Min
Max
Unit
tw(NWE)
FSMC_NWE low width
4THCLK–1
4THCLK+ 3
ns
tv(NWE-D)
FSMC_NWE low to FSMC_D[15-0] valid
-
0
ns
th(NWE-D)
FSMC_NWE high to FSMC_D[15-0] invalid
3THCLK –2
-
ns
td(D-NWE)
FSMC_D[15-0] valid before FSMC_NWE high
5THCLK–3
-
ns
td(ALE-NWE)
FSMC_ALE valid before FSMC_NWE low
-
3THCLK
ns
th(NWE-ALE)
FSMC_NWE high to FSMC_ALE invalid
3THCLK–2
-
ns
Table 87. DCMI characteristics(1)
Symbol
ParameterMin
Max
Unit
Frequency ratio DCMI_PIXCLK/fHCLK
-0.4
DCMI_PIXCLK
Pixel clock input
-
54
MHz
Dpixel
Pixel clock input duty cycle
30
70
%
MS32414V2
DCMI_PIXCLK
tsu(VSYNC)
tsu(HSYNC)
DCMI_HSYNC
DCMI_VSYNC
DATA[0:13]
1/DCMI_PIXCLK
th(HSYNC)
th(HSYNC)
tsu(DATA) th(DATA)



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