19/37

M25PE10, M25PE20

Page Program (PP)

The Page Program (PP) instruction allows Bytes

to be programmed in the memory (changing bits

from 1 to 0, only). Before it can be accepted, a

Write Enable (WREN) instruction must previously

have been executed. After the Write Enable

(WREN) instruction has been decoded, the device

sets the Write Enable Latch (WEL).

The Page Program (PP) instruction is entered by

driving Chip Select (S) Low, followed by the in-

struction code, three address Bytes and at least

one data Byte on Serial Data Input (D). If the 8

least significant address bits (A7-A0) are not all

zero, all transmitted data exceeding the ad-

dressed page boundary roll over, and are pro-

grammed from the start address of the same page

(the one whose 8 least significant address bits

(A7-A0) are all zero). Chip Select (S) must be driv-

en Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 15.

If more than 256 Bytes are sent to the device, pre-

viously latched data are discarded and the last 256

data Bytes are guaranteed to be programmed cor-

rectly within the same page. If less than 256 Data

Bytes are sent to device, they are correctly pro-

grammed at the requested addresses without hav-

ing any effects on the other Bytes of the same

page.

For optimized timings, it is recommended to use

the Page Program (PP) instruction to program all

consecutive targeted Bytes in a single sequence

versus using several Page Program (PP) se-

quences with each containing only a few Bytes

(see AC Characteristics (33MHz operation)).

Chip Select (S) must be driven High after the

eighth bit of the last data Byte has been latched in,

otherwise the Page Program (PP) instruction is not

executed.

As soon as Chip Select (S) is driven High, the self-

is initiated. While the Page Program cycle is in

progress, the Status Register may be read to

check the value of the Write In Progress (WIP) bit.

The Write In Progress (WIP) bit is 1 during the self-

timed Page Program cycle, and is 0 when it is

completed. At some unspecified time before the

cycle is complete, the Write Enable Latch (WEL)

bit is reset.

A Page Program (PP) instruction applied to a page

that is Hardware Protected is not executed.

Any Page Program (PP) instruction, while an

Erase, Program or Write cycle is in progress, is re-

jected without having any effects on the cycle that

is in progress.

Figure 15. Page Program (PP) Instruction Sequence

Note: 1. Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the M25PE10.

2. 1

≤n ≤256

C

D

AI04044

S

42

41

43 44 45 46 47 48 49 50

52 53 54 55

40

C

D

S

23

2

1

3456789 10

28 29 30 31 32 33 34 35

22 21

3210

36 37 38

Instruction

24-Bit Address

0

765432

0

1

Data Byte 1

39

51

765432

0

1

Data Byte 2

765432

0

1

Data Byte 3

Data Byte n

765432

0

1

MSB

MSB

MSB

MSB

MSB