P80C32 datasheet(42/62 Pages) PHILIPS

42 / 62 page

Philips Semiconductors

Product data

P80C3xX2; P80C5xX2;

P87C5xX2

80C51 8-bit microcontroller family

4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),

low power, high speed (30/33 MHz)

2003 Jan 24

AC ELECTRICAL CHARACTERISTICS (6-CLOCK MODE, 5 V

±10% OPERATION)

Tamb = 0 °C to +70 °C or –40 °C to +85 °C ; VCC = 5 V ±10%, VSS = 0 V1,2,3,4,5

Symbol

Figure

Parameter

Limits

16 MHz Clock

Unit

MIN

MAX

MIN

MAX

1/tCLCL

Oscillator frequency

–

MHz

tLHLL

ALE pulse width

tCLCL–8

–

54.5

–

tAVLL

Address valid to ALE low

0.5 tCLCL –13

–

18.25

–

tLLAX

Address hold after ALE low

0.5 tCLCL –20

–

11.25

–

tLLIV

ALE low to valid instruction in

–

2 tCLCL –35

–

tLLPL

ALE low to PSEN low

0.5 tCLCL –10

–

21.25

–

tPLPH

PSEN pulse width

1.5 tCLCL –10

–

83.75

–

tPLIV

PSEN low to valid instruction in

–

1.5 tCLCL –35

–

58.75

tPXIX

Input instruction hold after PSEN

–

tPXIZ

Input instruction float after PSEN

–

0.5 tCLCL –10

–

21.25

tAVIV

Address to valid instruction in

–

2.5 tCLCL –35

–

121.25

tPLAZ

PSEN low to address float

–

Data Memory

tRLRH

RD pulse width

3 tCLCL –20

–

167.5

–

tWLWH

WR pulse width

3 tCLCL –20

–

167.5

–

tRLDV

RD low to valid data in

–

2.5 tCLCL –35

–

121.25

tRHDX

Data hold after RD

–

tRHDZ

Data float after RD

–

tCLCL –10

–

52.5

tLLDV

ALE low to valid data in

–

4 tCLCL –35

–

215

tAVDV

Address to valid data in

–

4.5 tCLCL –35

–

246.25

tLLWL

28, 29

ALE low to RD or WR low

1.5 tCLCL –15

1.5 tCLCL +15

78.75

108.75

tAVWL

28, 29

Address valid to WR low or RD low

2 tCLCL –15

–

110

–

tQVWX

Data valid to WR transition

0.5 tCLCL –25

–

6.25

–

tWHQX

Data hold after WR

0.5 tCLCL –15

–

16.25

–

tQVWH

Data valid to WR high

3.5 tCLCL –5

–

213.75

–

tRLAZ

RD low to address float

–

tWHLH

28, 29

RD or WR high to ALE high

0.5 tCLCL –10

0.5 tCLCL +10

21.25

41.25

External Clock

tCHCX

High time

0.4 tCLCL

tCLCL – tCLCX

–

tCLCX

Low time

0.4 tCLCL

tCLCL – tCHCX

–

tCLCH

Rise time

–

tCHCL

Fall time

–

Shift register

tXLXL

Serial port clock cycle time

6 tCLCL

–

375

–

tQVXH

Output data setup to clock rising edge

5 tCLCL –25

–

287.5

–

tXHQX

Output data hold after clock rising edge

tCLCL –15

–

47.5

–

tXHDX

Input data hold after clock rising edge

–

tXHDV

Clock rising edge to input data valid

–

5 tCLCL –133

–

179.5

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN=100 pF, load capacitance for all outputs = 80 pF

3. Interfacing the microcontroller to devices with float time up to 45ns is permitted. This limited bus contention will not cause damage to port 0

drivers.

4. Parts are guaranteed by design to operate down to 0 Hz.

5. Data shown in the table are the best mathematical models for the set of measured values obtained in tests. If a particular parameter

calculated at a customer specified frequency has a negative value, it should be considered equal to zero.

P80C32 Datasheet(PDF) 42 Page - NXP Semiconductors

P80C32 Datasheet(HTML) 42 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Datasheet Download

Link URL