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74LVC373APW Datasheet(PDF) 13 Page - Nexperia B.V. All rights reserved |
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74LVC373APW Datasheet(HTML) 13 Page - Nexperia B.V. All rights reserved |
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13 / 15 page ![]() Nexperia 74LVC373A Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 12. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC373A v.5 20210827 Product data sheet - 74LVC373A v.4 Modifications: • Section 1 and Section 2 updated. • Type number 74LVC373ADB (SOT339-1/SSOP20) removed. • Fig. 9 and Fig. 11 corrected. 74LVC373A v.4 20200824 Product data sheet - 74LVC373A v.3 Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. • Table 4: Derating values for Ptot total power dissipation have been updated. • Package outline drawing of SOT764-1 (Fig. 15) updated. 74LVC373A v.3 20121122 Product data sheet - 74LVC373A v.2 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 4, Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage ranges. 74LVC373A v.2 20030519 Product specification - 74LVC373A v.1 74LVC373A v.1 19980729 Product specification - - 74LVC373A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 — 27 August 2021 13 / 15 |
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