TMP112ASLASHBSLASHN datasheet(8/47 Pages) TI1

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6.6 Timing Requirements

See the Two-Wire Timing Diagrams section for timing diagrams.

FAST MODE

FAST MODE PLUS

HIGH-SPEED MODE

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

f(SCL)

SCL operating frequency

TMP112A/B/N

0.001

0.4

TBD

0.001

2.85

MHz

TMP112Dx

0.001

0.4

0.001

TBD

t(BUF)

Bus-free time between

STOP and START

conditions

600

–

500

160

–

t(HDSTA)

Hold time after repeated

START condition.

After this period, the first

clock is generated.

600

–

260

160

–

t(SUSTA)

Repeated START condition

setup time

600

–

260

160

–

t(SUSTO) STOP condition setup time

600

–

260

160

–

t(HDDAT) Data hold time

100

900

150

105

t(SUDAT) Data setup time

100

–

t(LOW)

SCL clock low period

V+

1300

–

500

210

–

t(HIGH)

SCL clock high period

600

–

260

–

tFD

Data fall time

–

300

120

–

tRD

Data rise time

–

300

–

120

–

SCLK ≤ 100 kHz

–

1000

–

tFC

Clock fall time

–

300

–

120

–

tRC

Clock rise time

–

300

–

120

–

6.7 Timing Diagrams

SCL

SDA

(LOW)

(HDSTA)

(HDDAT)

(SUDAT)

(HIGH)

(SUSTA)

(SUSTO)

(BUF)

Figure 6-1. Two-Wire Timing Diagram

TMP112

SBOS473J – MARCH 2009 – REVISED FEBRUARY 2024

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