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 2005 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC4614

Applications Information (Cont.)

is given by:

2

2

)

(

)

1

(

IN

o

IN

RMS

I

I

D

I

D

I

-

×

+

×

-

=

rent, and D is the duty cycle. Choosing low ESR input

capacitors will help maximize ripple rating for a given size.

Bootstrap Circuit

Bootstrap Circuit

Bootstrap Circuit

Bootstrap Circuit

Bootstrap Circuit

The SC4614 uses an external bootstrap circuit to pro-

vide a voltage at the BST pin for the top MOSFET drive.

This voltage, referring to the Phase Node, is held up by a

bootstrap capacitor. Typically, it is recommended to use

a 1uF ceramic capacitor with 16V rating and a commonly

available diode IN4148 for the bootstrap circuit.

Filters for Supply Power

Filters for Supply Power

Filters for Supply Power

Filters for Supply Power

Filters for Supply Power

For each pin of DRV and Vcc, it is recommended to use a

1uF/16V ceramic capacitor for decoupling. In addition,

place a small resistor (10 ohm) in between the Vcc pin

and the supply power for noise reduction.

CONTROL LOOP DESIGN

CONTROL LOOP DESIGN

CONTROL LOOP DESIGN

CONTROL LOOP DESIGN

CONTROL LOOP DESIGN

The goal of compensation is to shape the frequency re-

sponse charateristics of the buck converter to achieve a

better DC accuracy and a faster transient response for

the output voltage, while maintaining the loop stability.

The block diagram in Fig. 3 represents the control loop

of a buck converter designed with the SC4614. The con-

trol loop consists of a compensator, a PWM modulator,

and a LC filter.

The LC filter and PWM modulator represent the small

signal model of the buck converter operating at fixed

switching frequency. The transfer function of the model

is given by:

LC

s

R

sL

C

sR

V

V

V

V

ESR

m

IN

C

O

2

/

1

1

+

+

+

×

=

of the 500kHz ramp, and R is the equivalent load.

L

Vo

Co

SC4614 AND MOSFETS

FB

OUT

COMP

PWM

MODULAT OR

REF

+

-

EA

Resr

Zf

Zs

Vc

Fig. 3. Block diagram of the control loop

The model is a second order system with a finite DC gain,

a complex pole pair at Fo, and an ESR zero at Fz, as

shown in Fig. 4. The locations of the poles and zero are

determined by:

LC

F

O

1

=

C

R

F

ESR

Z

1

=

The compensator in Fig. 3 includes an error amplifier and

impedance networks Zf and Zs. It is implemented by the

circuit in Fig. 5. The compensator provides an integrator,

double poles and double zeros. As shown in Fig. 4, the

integrator is used to boost the gain at low frequency.

Two zeros are introduced to compensate excessive phase

lag at the loop gain crossover due to the integrator

(-90deg) and complex pole pair (-180deg). Two high fre-

quency poles are designed to compensate the ESR zero

and attenuate high frequency noise.