ADIN6310BBCZ datasheet(52/86 Pages) AD

52 / 86 page

Data Sheet

ADIN3310/ADIN6310

HOST INTERFACE

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Rev. A | 52 of 86

1 P2 through P0 select the port for SGMII, RMII, and RGMII host interface, see Table 23.

2 x = Don't care.

3 TIMER0, TIMER1, and SPI_SS have internal pull-ups. TIMER2, TIMER3 and SPI_SIO0 to SPI_SIO2 have internal pull-downs. The default configuration is a standard SPI

when no external host strapping is used. To configure a different host interface, use the external pull-up and pull-down resistor values per Table 24.

4 Ensure that the clock delays are configured correctly to interface with the host and PHY or MAC. Delay is added at only one stage in the transmit and receive paths,

typically at the receiving side. For MAC interfaces that do not have the capability to add delay, the switch host strapping supports adding delays on both sides.

5 ds = Drive strength. Two drive strength options are available for the host interface (high or low). When ds = 1, this corresponds to the higher drive strength. Drive strength

for other ports can be configured through the Software Driver API, which is available from the ADIN6310 product page.

The default mode is the standard SPI interface based on internal

pull-up and pull-down resistors. External pull-up and pull-down

resistors are required to override the default values and are detailed

in Table 24.

After initial communication is established, software can establish

the other means of communication for applications that use two

interfaces between switch and host, one for control traffic (strapping

interface) and one for data traffic.

Table 23. Boot Strapping Pin Configuration—Host Port Selection

Function and Host Port

Mnemonic

SPI_SIO2

SPI_SIO1

SPI_SIO0

SPI, Dual SPI and Quad SPI (No

Ethernet Port Selected)

ds1

Port 0 RMII or RGMII

Port 1 RMII, RGMII, or SGMII

Port 2 RMII, RGMII, or SGMII

Port 3 RMII, RGMII, or SGMII

Port 4 RMII, RGMII, or SGMII

Port 5 RMII or RGMII

Reserved

1 ds = Drive strength. Two drive strength options are available for the host inter-

face (high or low). When ds = 1, this corresponds to the highest drive strength.

Drive strength for other ports can be configured through the SES_SetGpio-

DriveStrength() API, which is available in the SES_switch.h file from the

ADIN6310 product page.

Because the TIMERx and SPI_SIOx pins are on the VDDIO_A

power domain, external strapping resistors should be pulled to

VDDIO_A.

Ensure that these pins are static and in the correct state during

the hardware latch after reset. Table 24 provides information on

the external resistor values required for each pin to overcome the

internal strapping.

Table 24. External Strapping Resistor Values

Mnemonic

Default

External Series Resistor Value

TIMER0

Pull-down <2.5 kΩ to latch a value 0

TIMER1

Pull-down <2.5 kΩ to latch a value 0

TIMER2

Pull-up <3.3 kΩ to latch a value 1

TIMER3

Pull-up <3.3 kΩ to latch a value 1

SPI_SS

Pull-down <400 Ω to latch a value 0

Table 24. External Strapping Resistor Values (Continued)

Mnemonic

Default

External Series Resistor Value

SPI_SIO0

Pull-up <10 kΩ to latch a value 1

SPI_SIO1

Pull-up <10 kΩ to latch a value 1

SPI_SIO2

Pull-up <10 kΩ to latch a value 1

TIMER INPUTS AND OUTPUTS

There are four timer pins (TIMER0 to TIMER3) that are dedicated

to timer and interrupt functions, with TIMER0 providing the interrupt

function for the switch SPI. The function of these pins is controlled

from the packet assist engine. There are four TSN timer outputs,

four legacy timer outputs, two IEEE 1588 outputs, and two input

captures as detailed in Table 25.

The timer pins can alternatively be configured in GPIO mode and

use as GPIOs as required.

Table 25. Timer Functions

Timer

Mnemonic

Function

GPIO Mode

TIMER0/INT

TSN timer, industrial Ethernet engine

multiprotocol timer, interrupt

GPIO4

TIMER1

TSN timer, industrial Ethernet engine

multiprotocol timer

GPIO5

TIMER2

TSN timer, industrial Ethernet engine

multiprotocol timer, IEEE 1588 timer, timer input

GPIO6

TIMER3

TSN timer, industrial Ethernet engine

multiprotocol timer, IEEE 1588 timer, timer input

GPIO7

GPIO

There are four dedicated GPIO pins available in the switch. Their

function is configured by the packet assist engine.

HARDWARE RESET

The RESET_N is an active low input to the switch and resides on

the VDDIO_A power supply domain. The RESET_N pin must be

asserted low for a minimum of 100 μs after all power supplies are

at their nominal values. After power on, when RESET_N is brought

high and stays high, the external strapping pin states are latched.

During operation, to perform a hardware reset, the RESET_N pin

must be driven low for a minimum 10 μs. When asserted low, all

output pins are driven to a High-Z state.

ADIN6310BBCZ Datasheet(PDF) 52 Page - Analog Devices

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