 2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA

Appnote 28

www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)

OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany

www.osram-os.com • +49-941-202-7178

4

May 31, 2000-13

Conclusion

Note that although other manufacturers’ products are used in

the examples, this application note does not imply specific

endorsement, or warranty of other manufacturer's products by

OSRAM. The interface schemes shown demonstrate the sim-

plicity of using the DLO4135/DLG4137 dot matrix Intelligent Dis-

Program Listing

1

; BY DAN WATSON

2

; TO DO LAMP TEST, SET 100% BRIGHTNESS

3

; AND WRITE ‘SIEMENS*’

4

5

; P3.0 = BLO\

6

; P3.1 = BL1\

7

; P3.2 = LT\

8

; P3.6 = WR\

9

10

; RO = DIGIT ADDRESS ( CHIP ENABLES – CE\ )

11

; R1 = DIGIT COUNTER

12

; R7 = R6 = R5 = WAIT REGISTERS

13

14

0000

.ORG 00H

15

0000

02 00 03

INIT:JMP BEGIN

16

0003

12 00 24

BEGIN:CALL WAIT1

; DELAY FOR uC TO STABILIZE

17

0006

75 B0 00

MOV P3,#00H

; LAMP TEST

18

0009

12 00 24

CALL WAIT1

; DISPLAY LT\ FOR A WHILE

19

000C

75 B0 07

MOV P3,#07H

; SET ALL 8 DISPLAYS TO 100% BRT

20

000F

00

NOP

21

0010

00

NOP

22

0011

78 00

MOV R0,#00H

; DIGIT 7 ADDRESS

23

0013

79 08

MOV R1,#08H

; 8 DIGIT COUNTER

24

0015

74 00

MOV A,#00H

; CLEAR ACC.

25

0017

90 00 37

MOV DPTR,#TEXT

; ADDRESS OF THE MESSAGE

26

001A

93

WRT:MOVC A,@A+DPTR

; LOAD FIRST CHAR. INTO THE ACC.

27

001B

F2

MOVX @R0,A

; DIGIT ADDRESS AND DATA WRITE

28

001C

A3

INC DPTR

; NEXT CHARACTER ADDRESS

29

001D

08

INC R0

; NEXT DIGIT (6) ADDRESS

30

001E

E4

CLR A

31

001F

D9 F9

DJNZ R1,WRT

; WRITE ALL 8 CHAR.

32

0021

00

GO:NOP

33

0022

01 21

JMP GO

; MESSAGE ALWAYS ON

34

0024

35

0024

36

0024

7F 88

WAIT1:MOV R7,#88H

; DELAY LOOPS

37

0026

00

NOP

38

0027

7E FF

WAIT2:MOV R6,#FFH

39

0029

00

NOP

40

002A

7D FF

WAIT3:MOV R5,#FFH

41

002C

00

NOP

42

002D

DD FE

DJNZ R5,$

43

002F

00

NOP

44

0030

DE F8

DJNZ R6,WAIT3

45

0032

00

NOP

46

0033

DF F2

DJNZ R7,WAIT2

47

0035

00

NOP

48

0036

22

RET

49

50

0037

53 49 45 4D 45

TEXT:DB ‘SIEMENS*’

003C

4E 53 2A

51

003F

52

003F

.END

play. Slight timing differences may be encountered for various

microprocessors, but can be resolved using similar methods as

those used when using interfacing microprocessors with various

RAMs. The techniques used in the examples were shown for

their generality. The user will undoubtedly invent other schemes

to optimize his particular system to its requirements.