SLAS367 datasheet(13/56 Pages) TI2

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3–1

3 Functional Description

3.1

Operating Frequencies (see Notes)

The sampling frequency is the frequency of the frame sync (FS) signal whose falling edge starts digital-data transfer

for both ADC and DAC. The sampling frequency is derived from the master clock (MCLK) input by the following

equations:

•

Coarse sampling frequency (default):

The coarse sampling is selected by programming P = 8 in the control register 4, which is the default

configuration of AIC15 on power-up or reset.

FS = Sampling (conversion) frequency = MCLK / (16

× M × N × 8)

•

Fine sampling frequency (see Note 5):

FS = Sampling (conversion) frequency = MCLK/ (16

× M × N × P)

NOTES:

1. Use control register 4 to set the following values of M, N, and P

2. M = 1,2, . . . ,128

3. N = 1,2, . . . ,16

4. P = 1,2, . . . ,8

5. The fine sampling rate needs an on-chip Delay Lock Loop (frequency multiplier) to generate internal clocks. The

DLL requires the relationship between MCLK and P to meet the following condition: 10 MHz

≤ (MCLK/P) ≤ 25 MHz

6. Both equations of FS require that the following conditions should be met:

S (M × N × P) ≥ (devnum × mode) if the FIR/IIR filter is not bypassed.

S [Integer(M/4) × N × P] ≥ (devnum × mode) if the FIR/IIR filter is bypassed.

where

devnum is the number of devices connecting in cascade

mode is equal to 1 for continuous data transfer mode and 2 for programming mode

EXAMPLE:

The MCLK comes from the DSP C5402’s CLKOUT and equals to 20.48 MHz and the conversion rate of 8 kHz is

desired. First, set P = 1 to satisfy the condition 5 so that (MCLK/P) = 20.48 MHz/1 = 20.48 MHz. Next, pick

M = 10 and N = 16 to satisfy condition 6 and derive 8 kHz for FS. That is,

FS = 20.48 MHz/ (16

× 10 × 16 × 1) = 8 kHz

3.2

Internal Architecture

3.2.1

Antialiasing Filter

The built-in antialiasing filter is a two-pole filter that has a 20-dB attenuation at 1 MHz.

3.2.2

Sigma-Delta ADC

The sigma-delta analog-to-digital converter is a sigma-delta modulator with 128-x oversampling. The ADC provides

high-resolution, low-noise performance using oversampling techniques. Due to the oversampling employed, only

single pole R-C filters are required on the analog inputs.

SLAS367 Datasheet(PDF) 13 Page - Texas Instruments

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