CY2SSTV857-32

Rev 1.0, November 21, 2006

Page 4 of 8

CLKIN

t

pd

Yx or FBIN

t

C(n+1)

Yx

t

C(n)

Figure 3. Cycle-to-cycle Jitter

PLL

FBIN

FBIN#

120

Ohm

120

Ohm

CLK

CLK#

DDR -

SDRAM

120

Ohm

VTR

VCP

0.3"

= 2.5"

= 0.6" (Split to Terminator)

DDR _SDRAM

represents a capacitive load

DDR -

SDRAM

FBOUT#

FBOUT

Output load capacitance for 2 DDR-SDRAM Loads: 5 pF< CL< 8 pF

Figure 4. Clock Structure # 1