25CS160-HSLASHST datasheet(18/53 Pages) MICROCHIP

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Preliminary

DS20007008B-page 18

25CS160

6.0

STATUS REGISTER

6.1

STATUS Register Bit Definition

The 25CS160 includes a 2-byte STATUS register,

which is a combination of six nonvolatile bits of

EEPROM and six volatile latches. The STATUS

shown in Register 6-1 and Register 6-2. These bits can

be read or modified by specific instructions that are

detailed in the subsequent sections.

STATUS REGISTER (BYTE 0)

R/W

U-0

R/W

R-0

WPEN

—

BP1

BP0

WEL

RDY/BSY

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

WPEN: Write-Protect Enable

1 = Write-Protect pin is enabled

0 = Write-Protect pin is ignored

bit 6-4

Unimplemented: Read as ‘0’

bit 3-2

BP[1:0]: Block Protection (see Table 6-2)

00 = No array write protection

01 = Upper quarter memory array protection

10 = Upper half memory array protection

11 = Entire memory array protection

bit 1

WEL: Write Enable Latch

1 = WREN instruction has been executed, and device is enabled for writing

0 = Device is not write-enabled

bit 0

RDY/BSY: Ready/Busy Status Latch

1 = Device is busy with an internal write cycle

0 = Device is ready for a new sequence

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