W150

Rev 1.0, November 24, 2006

Page 11 of 14

Duty Cycle

Measured on rising and falling edge at 1.5V

45

55

%

Jitter, Cycle-to-Cycle

Measured on rising edge at 1.5V. Maximum

difference of cycle time between two

adjacent cycles.

250

ps

Output Skew

Measured on rising edge at 1.5V

500

ps

CPU to PCI Clock Skew

Covers all CPU/PCI outputs. Measured on

rising edge at 1.5V. CPU leads PCI output.

1.5

4

ns

Frequency Stabilization

from Power-up (cold start)

Assumes full supply voltage reached within

1 ms from power-up. Short cycles exist prior

to frequency stabilization.

3ms

AC Output Impedance

Average value during switching transition.

Used for determining series termination

value.

15

IOAPIC0 and IOAPIC_F Clock Outputs (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Test Condition/Comments

CPU = 66.6/100 MHz

Unit

Min.

Typ.

Max.

f

Frequency, Actual

Frequency generated by crystal oscillator

14.31818

MHz

Output Rise Edge Rate

Measured from 0.4V to 2.0V

1

4

V/ns

Output Fall Edge Rate

Measured from 2.0V to 0.4V

1

4

V/ns

Duty Cycle

Measured on rising and falling edge at 1.25V

45

55

%

Frequency Stabilization

from Power-up (cold start)

Assumes full supply voltage reached within

1 ms from power-up. Short cycles exist prior to

frequency stabilization.

1.5

ms

AC Output Impedance

Average value during switching transition.

Used for determining series termination value.

15

REF0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Test Condition/Comments

CPU = 66.6/100 MHz

Unit

Min.

Typ.

Max.

f

Frequency, Actual

Frequency generated by crystal oscillator

14.318

MHz

Output Rise Edge Rate

Measured from 0.4V to 2.4V

0.5

2

V/ns

Output Fall Edge Rate

Measured from 2.4V to 0.4V

0.5

2

V/ns

Duty Cycle

Measured on rising and falling edge at 1.5V

45

55

%

Frequency Stabilization

from Power-up (cold

start)

Assumes full supply voltage reached within 1 ms from

power-up. Short cycles exist prior to frequency stabili-

zation.

3ms

AC Output Impedance

Average value during switching transition. Used for

determining series termination value.

25

SDRAM 0:15, _F Clock Outputs (Lump Capacitance Test Load = 30 pF)

Parameter

Description

Test Condition/Comments

CPU = 66.8 MHz

CPU = 100 MHz

Unit

Min.

Typ.

Max.

Min.

Typ.

Max.

t

P

Period

Measured on rising edge at 1.5V

15

15.5

10

10.5

ns

High Time

Duration of clock cycle above 2.4V

5.2

3.0

ns

Low Time

Duration of clock cycle below 0.4V

5.0

2.0

ns

Output Rise Edge Rate Measured from 0.4V to 2.4V

1

4

1

4

V/ns

Output Fall Edge Rate

Measured from 2.4V to 0.4V

1

4

1

4

V/ns

PCI Clock Outputs, PCI_F and PCI0:5 (Lump Capacitance Test Load = 30 pF) (continued)

Parameter

Description

Test Condition/Comments

CPU = 66.6/100 MHz

Unit

Min.

Typ.

Max.