C2901 datasheet(2/4 Pages) ETC2

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CAST C2901 Megafuction Datasheet

Pin Description

Name

Type

Description

Input

Clock

I[8:0]

Input

Instruction/Microcode

D[3:0]

Input

Data Input

A[3:0]

Input

A-port Address

B[3:0]

Input

B-port Address

Input

Carry In

Q0IN

Input

Shift Line – Q Register

RAM0IN

Input

Shift Line – RAM Stack

Q3IN

Input

Shift Line – Q Register

RAM3IN

Input

Shift Line – RAM Stack

Y[3:0]

Output

Data Output

Output

Carry Generate

Output

Carry Propagate

OVR

Output

Overflow

Output

ALU outputs are zero

Output

ALU MSB

CNP4

Output

Carry out

Q0OUT

Output

Shift Line – Q Register

RAM0OUT

Output

Shift Line – RAM Stack

Q3OUT

Output

Shift Line – Q Register

RAM3OUT

Output

Shift Line – RAM Stack

FEQEN

Output

ALU outputs are zero (control for Open Collector Output)

Q0EN

Output

Enable for Q0 Tristate Output

Q3EN

Output

Enable for Q3 Tristate Output

RAM0EN

Output

Enable for RAM0 Tristate Output

RAM3EN

Output

Enable for RAM3 Tristate Output

Functional Description

This section describes the Block Diagram below. A description of each of the blocks in the

diagram is given here.

Dual Port RAM

The internal memory is a 4 bit by 16 Dual Port RAM. It is addressed for writing by the B Port

and for reading by both the A and B Ports. The input data is defined by a microinstruction

decoded from 3 bits of the 9-bit I Port.

RAM Latch

These latches store the outputs of the Dual Port RAM. They are clocked using the CP input.

Q Register

This section describes the internal register. It is selected using the Instruction input (I) and

clocked with the CP input.

CAST, Inc.

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