Data Sheet

ADP1706/ADP1707/ADP1708

THEORY OF OPERATION

analog.com

Rev. B | 12 of 19

The ADP1706/ADP1707/ADP1708 are low dropout linear regulators

that use an advanced, proprietary architecture to provide high

power supply rejection ratio (PSRR) and excellent line and load

transient response with a small 4.7 µF ceramic output capacitor. All

devices operate from a 2.5 V to 5.5 V input rail and provide up to

1 A of output current. Supply current in shutdown mode is typically

100 nA.

Figure 27. Internal Block Diagram

Internally, the ADP1706/ADP1707/ADP1708 consist of a reference,

an error amplifier, a feedback voltage divider, and a PMOS pass

transistor. Output current is delivered via the PMOS pass device,

which is controlled by the error amplifier. The error amplifier com-

pares the reference voltage with the feedback voltage from the

output and amplifies the difference. If the feedback voltage is

lower than the reference voltage, the gate of the PMOS device

is pulled lower, allowing more current to pass and increasing the

output voltage. If the feedback voltage is higher than the reference

voltage, the gate of the PMOS device is pulled higher, allowing less

current to pass and decreasing the output voltage.

The ADP1706/ADP1707 are available in 16 fixed output voltage

options between 0.75 V and 3.3 V. The ADP1706 allows for

connection of an external soft start capacitor, which controls the

output voltage ramp during startup. The ADP1707 features a TRK

pin that allows the output voltage to follow the voltage at this pin.

The ADP1708 is available in an adjustable version with an output

voltage that can be set to between 0.8 V and 5.0 V by an external

voltage divider. All devices are controlled by an enable pin (EN).

SOFT START FUNCTION (ADP1706)

For applications that require a controlled startup, the ADP1706

provides a programmable soft start function. The programmable

soft start is useful for reducing inrush current upon startup and for

providing voltage sequencing. To implement a soft start, connect a

small ceramic capacitor from SS to GND. Upon startup, a 1.2 µA

current source charges this capacitor. The ADP1706 start-up output

voltage is limited by the voltage at SS, providing a smooth ramp-up

to the nominal output voltage. The soft start time is calculated by

TSS = VREF × (CSS/ISS)

(1)

where:

TSS is the soft start period.

VREF is the 0.8 V reference voltage.

CSS is the soft start capacitance from SS to GND.

ISS is the current sourced from SS (1.2 µA).

When the ADP1706 is disabled (using EN), the soft start capacitor

is discharged to GND through an internal 100 Ω resistor.

Figure 28. OUT Ramp-Up with External Soft Start Capacitor

The ADP1707 and ADP1708 have no pins for soft start; therefore,

the function is switched to an internal soft start capacitor, which sets

the soft start ramp-up period to approximately 48 µs. Note that the

ramp-up period is the time it takes OUT to go from 0% to 90% of

the nominal value and is different from the start-up time in Table

1, which is the time between the rising edge of EN to OUT being

at 90% of the nominal value. For the worst-case output voltage

of 5 V, using the suggested 4.7 µF output capacitor, the resulting

input inrush current is approximately 490 mA, which is less than the

maximum 1 A load current.

Figure 29. OUT Ramp-Up with Internal Soft Start

ADJUSTABLE OUTPUT VOLTAGE (ADP1708)

The ADP1708 can have its output voltage set over a 0.8 V to 5.0 V

range. The output voltage is set by connecting a resistive voltage

divider from OUT to ADJ. The output voltage is calculated by

VOUT = 0.8 V (1 + R1/R2)

(2)