ZPSD413A1 datasheet(79/123 Pages) STMICROELECTRONICS

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Port Configuration

Reset

Stand-by Mode

Port I/O

Input

Unchanged

ZPLD Output

Active

Depend on Inputs to the ZPLD

Address Out

Tri-stated

Not Defined

Data Port

Tri-stated

Peripheral I/O

Tri-stated

PSD4XX Family

Device

Reset State

Control

Port A, B, C, D, E

Set to “0”

(Address Out Mode)

Data Out

(data or address)

Port A, B, C, D, E

Set to “0”

Direction

Port A, B, C, D, E

Set to “0” – Input Mode

Open Drain

Port C, D

Set to “0” – CMOS Outputs

Page Register

Page Logic

Set to “0”

PMMR0, PMMR1

Power Management Unit

Set to “0”

Volatile Memory

Set to “0”

System

Configuration

(cont.)

Table 24. Registers Reset Values

Table 25. I/O Pin Status During Reset and Standby Mode

12.1 Reset Input

The reset input to the PSD4XX (RESET) is an active low signal which resets some of the

internal devices and configuration registers. The Timing Diagram in the AC/DC

characterization section shows the reset signal timing requirement. The active low range

has a minimum T1 duration. After the rising edge of RESET, the PSD4XX remains in

reset during T2 range. (See Figure 48). The PSD4XX must be reset at power up before it

can be used.

12.2 ZPLD and Memory During Reset

While the Reset Input is active, the ZPLD generates outputs as defined in the PSDabel

equations. The EPROM and SRAM blocks respond to the microcontroller bus cycle during

reset, but the data is not guaranteed.

12.3 Register Values During and After Reset

Table 24 summarizes the status of the volatile register values during and after reset.

The default values of the volatile registers are “0” after reset.

12.4 ZPLD Macrocell Initialization

The D flip flops in the macrocells in the GPLD can be cleared by:

t A product term (.RE) defined by the user in PSDabel, or

t The MACRO-RST (Reset) input, enabled and defined in PSDabel.

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