T80C5112-RKFCV datasheet(39/97 Pages) ATMEL

39 / 97 page

Rev. B - November 10, 2000

Preliminary

T80C5112

Table 20. BDRCON Register

BDRCON - Baud Rate Control Register (9Bh)

Reset Value = XXX0 0000b

BRR

TBCK

RBCK

SPD

SRC

Bit

Number

Bit

Mnemonic

Description

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit.

BRR

Baud Rate Run Control bit

Clear to stop the internal Baud Rate Generator.

Set to start the internal Baud Rate Generator.

TBCK

Transmission Baud rate Generator Selection bit for UART

Clear to select Timer 1 or Timer 2 for the Baud Rate Generator.

Set to select internal Baud Rate Generator.

RBCK

Reception Baud Rate Generator Selection bit for UART

Clear to select Timer 1 or Timer 2 for the Baud Rate Generator.

Set to select internal Baud Rate Generator.

SPD

Baud Rate Speed Control bit for UART

Clear to select the SLOW Baud Rate Generator.

Set to select the FAST Baud Rate Generator.

SRC

Baud Rate Source select bit in Mode 0 for UART

Clear to select FOSC/12 as the Baud Rate Generator (FOSC/6 in X2 mode).

Set to select the internal Baud Rate Generator for UARTs in mode 0.

T80C5112-RKFCV Datasheet(PDF) 39 Page - ATMEL Corporation

T80C5112-RKFCV Datasheet(HTML) 39 Page - ATMEL Corporation

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