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T80C5112-RKSCL Datasheet(PDF) 90 Page - ATMEL Corporation |
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T80C5112-RKSCL Datasheet(HTML) 90 Page - ATMEL Corporation |
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90 / 97 page  90 Rev. B - November 10, 2000 Preliminary T80C5112 18.6.6. External Data Memory Read Cycle Figure 42. External Data Memory Read Cycle 18.6.7. Serial Port Timing - Shift Register Mode Table 62. AC Parameters for a Fix Clock Table 61. Symbol Description Symbol Parameter TXLXL Serial port clock cycle time TQVHX Output data set-up to clock rising edge TXHQX Output data hold after clock rising edge TXHDX Input data hold after clock rising edge TXHDV Clock rising edge to input data valid Speed -V X2 mode 30 MHz 60 MHz equiv. -V standard mode 40 MHz -L X2 mode 20 MHz 40 MHz equiv. -L standard mode 30 MHz Units Symbol Min Max Min Max Min Max Min Max TXLXL 200 300 300 400 ns TQVHX 117 200 200 283 ns TXHQX 13 30 30 47 ns TXHDX 0 0 0 0 ns TXHDV 34 117 117 200 ns ALE PSEN RD PORT 0 PORT 2 A0-A7 DATA IN ADDRESS OR SFR-P2 TAVWL TLLWL TRLAZ ADDRESS A8-A15 OR SFR P2 TRHDZ TWHLH TRLRH TLLDV TRHDX TAVDV TLLAX TRLDV |
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