6

LTC1502-3.3

1

2

3

1502-3.3 F01

4

ON OFF

8

7

100

Ω

6

5

GND

10

µF

LTC1502-3.3

C2

Figure 1. Pull-Down Circuitry for Shutdown

back into active mode. If no external pull-down is present

during the Hi-Z interval, the internal pull-up current will

ing the part in active mode.

The shutdown feature can be used to prevent charge pump

switching during noise sensitive intervals. Since the charge

pump oscillator is disabled during shutdown, output switch-

ing noise can be eliminated while the external pull-down is

active. The LTC1502-3.3 takes between 20

µs and 50µs to

switch from shutdown to active mode once the pull-down

device has been turned off (assuming a 100pF external

by a factor of five at the expense of 10

µA or so of additional

shutdown current. To maintain regulation, a sufficiently

large output capacitor must be used to prevent excessive

there must be adequate time for the charge pump to

recharge the output capacitor while the part is active. In

other words, the average load current must be low enough

for the LTC1502-3.3 to maintain a 3.3V output while the

part is active.

Capacitor Selection

For best performance, it is recommended that low ESR

either ceramic or tantalum and should be 10

µF or greater.

If the input source impedance is very low (< 0.5

may not be needed. Ceramic capacitors are recommended

for the flying capacitors C1 and C3 with values of 0.47

µF

to 2.2

µF. Smaller values may be used in low output current

Output Ripple

Normal LTC1502-3.3 operation produces voltage ripple

regulation. Low frequency ripple exists due to the hyster-

esis in the sense comparator and propagation

delays in the charge pump enable/disable circuits. High

frequency ripple is also present mainly from the ESR

(equivalent series resistance) in the output capacitor. Typi-

50mV peak-to-peak with a low ESR 10

µF output capacitor.

The magnitude of the ripple voltage depends on several

factors. High input voltages increase the output ripple

Large output current load and/or a small output capacitor

(<10

µF) results in higher ripple due to higher output

voltage dV/dt. High ESR capacitors (ESR > 0.5

Ω) on the

with every clock cycle.

There are several ways to reduce the output voltage ripple.

charging and discharging dV/dt and the lower ESR typi-

cally found with higher value (larger case size) capacitors.

A low ESR ceramic output capacitor will minimize the high

frequency ripple, but will not reduce the low frequency

ripple unless a high capacitance value is chosen. A reason-

able compromise is to use a 10

µF to 22µF tantalum

capacitor in parallel with a 1

µF to 3.3µF ceramic capacitor

An RC filter may also be used to reduce high frequency

voltage spikes (see Figure 2).

LTC1502-3.3

10

µF

TANTALUM

1

µF

CERAMIC

2

Ω

8

8

10

µF10µF

1502-3.3 F02

+

+

+

LTC1502-3.3

Figure 2. Output Ripple Reduction Techniques