November 2006

P2005A/S

rev 1.3

Low Frequency EMI Reduction IC

2 of 8

Notice: The information in this document is subject to change without notice.

XOUT

1

2

3

4

5

6

7

8

P2005A/S

XIN /CLK

DIV2

VSS

SR0

SSON#

ModOUT

VDD

Pin Configuration

Pin Description

Pin#

Pin

Name

Type

Description

1

XIN/CLK

I

Connect to crystal or clock.

2

XOUT

O

Crystal output.

3

DIV2

I

Digital logic input used to select normal output mode or divide-by-two output mode. When

this pin is HIGH, the frequency of the output clock is the same as the input clock

frequency. When it is tied low, the output frequency is half the input clock frequency. This

pin has an internal pull-up resistor.

4

VSS

P

Ground to entire chip. Connect to system ground.

5

SR0

I

Digital logic input used to select Spreading Range Refer Modulation Output and Spreading

Range Selection Table. This pin has an internal pull-up resistor.

6

SSON#

I

Digital logic input used to enable Spread Spectrum function (Active LOW). Spread

Spectrum function enabled when LOW, disabled when HIGH. This pin has an internal pull-

low resistor.

7

ModOUT

O

Spread spectrum clock output.

8

VDD

P

Power supply for the entire chip (+3.3V or 5.0V)

Output Frequency Selections

Input Frequency

8MHz

12MHz

16MHz

20MHz

24MHz

28MHz

32MHz

0 (1/2 X)

4MHz

6MHz

8MHz

10MHz

12MHz

14MHz

16MHz

DIV2

1 (1X)

8MHz

12MHz

16MHz

20MHz

24MHz

28MHz

32MHz

Output

Frequency

Frequency Deviation Selections as a Function of Input Frequency

Input Frequency Range

P/N

SR0

8MHz

12MHz

16MHz

20MHz

24MHz

28MHz

32MHz

Modulation Rate

(KHz)

0

± 3.0%

± 2.5%

± 2.0%

± 1.8%

± 1.5%

± 1.5%

± 1.3%

P2005A

1

± 2.5%

± 2.0%

± 1.8%

± 1.5%

± 1.3%

± 1.3%

± 1.0%

0

± 1.8%

± 1.5%

± 1.2%

± 1.1%

± 0.9%

± 0.9%

± 0.8%

P2005S

1

± 1.5%

± 1.2%

± 1.1%

± 0.9%

± 0.8%

± 0.8%

± 0.6%