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Revision 1.03

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AS1526/AS1527

Unlike the SPI interface, which requires two 1-byte reads to acquire the 10 data bits from the AS1526/AS1527, QSPI

allows the minimum number of clock cycles necessary to clock in the data. The devices require 11 clock cycles from

the microprocessor to clock out the 10 data bits with no trailing zeros or 13 clock cycles from the microprocessor to

clock out the 10 data bits and two sub-bits with no trailing zeros (see Figure 36).

Note:

The maximum clock frequency to ensure compatibility with QSPI is 2.097MHz.

Figure 36. QSPI Serial Interface Timing (CPOL = CPHA = 0)

Layout Considerations

The AS1526/AS1527 require proper layout and design procedures for optimum performance.

!

Use printed circuit boards; wirewrap boards should not be used.

!

Separate analog and digital traces from each other. Analog and digital traces should not run parallel to each other

(especially clock traces).

!

Digital traces should not run beneath the AS1526/AS1527.

!

Use a single-point analog ground at GND, separate from the digital ground (see Figure 37). Connect all other ana-

log grounds and DGND to this star ground point for further noise reduction. No other digital system ground should

be connected to this single-point analog ground. The ground return to the power supply for this ground should be

low impedance and as short as possible for noise-free operation.

!

this supply to the single-point analog ground with 0.1µF and 4.7µF bypass capacitors (see Figure 37). The bypass

capacitors should be placed as close to the device as possible for optimum power supply noise-rejection. If the

power supply is very noisy, a 10

Ω resistor can be connected as a low-pass filter to attenuate supply noise.

Figure 37. Recommended Ground Design

SCLK

CSN

DOUT

EOC

LSB

MSB

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

S1

S0

High-Z

when CSN

is High

AS1526/

AS1527

Power

Supplies

Digital

Circuitry

0.1µF

+

4.7µF

10

Ω

(Optional)

GND

GND

+3V

1

5

GND

+3V

+3V

DGND